Hardware Description Language Chisel & Diplomacy Deeper diveAre you using Chisel? A hardware building language based on Scala. Not a high-level synthesis language. SiFive's RISC-V IP use Chisel Rocket-Chip : https://github.com/chipsalliance/rocket-chip BOOM : https://github.com/riscv-boom/riscv-boom…
Where to start with RISC-VOriginally posted on Medium How to get started, where to contribute, and what to do next RISC-V made the news recently when BeagleBoard.org revealed the…
Overview of Diplomacy for writing effective hardware design language Chisel (Japanese)ハードウェア記述言語Chiselをもっともっと活用するためのDiplomacy概説 発表者：msyksphinz (FPGA開発日記著者) @msyksphinz_dev https://msyksphinz.hatenablog.com Chisel使ってますか？ Scalaをベースとしたハードウェア構築言語. 高位合成言語ではない SiFiveのRISC-V IPで採用されている Rocket-Chip : https://github.com/chipsalliance/rocket-chip BOOM : https://github.com/riscv-boom/riscv-boom Chiselの基礎 : 「Chiselを始めたい人に読んで欲しい本」 https://nextpublishing.jp/book/12162.html ChiselがVerilogを生成するまで ChiselはScalaのDSLなので、Chisel CompilerはScalaで記述してある Chisel CompilerはFIR (Flexible Interpretation Representation)と呼ばれる中間言語を生成する…
RISC-V CPU Performance | Maven SiliconThis video explains how Maven Silicon measures the CPU performance and how we try to improve the processor performance by improving its clock frequency and…
Let’s Make RISC-V Connected Systems Synonymous with SecurityThis blog was submitted by Silex Insight. If you are designing systems based on a RISC-V architecture, for example to run highly connected applications,…
RISC-V Microarchitecture for Kids??!! | Steve Hoover, Redwood EDALast month I had the great pleasure of sharing a blog post about Nicholas Sharkey, an amazing 13 year-old who participated with graduate students and…
What is Processor Core Complexity?This blog was originally published on the Codasip blog. The more complex a processor core, the larger the area and power consumption. But increasing…
What is Needed to Support an Operating System?This blog was originally published on the Codasip blog. For each embedded product, software developers need to consider whether they need an operating system;…
Understanding the Performance of Processor IP CoresThis blog was originally published on the Codasip blog. Looking at any processor IP, you will find that their vendors emphasise PPA (performance, power…
RPC DRAM support in open source DRAM controllerOriginal content published October 28, 2020 on the Antmicro blog. The Internet of Things is one of the areas that is hugely benefiting from miniaturization…
13-Year-Old, Nicholas Sharkey, Creates a RISC-V CoreOne of my great pleasures operating my EDA startup, Redwood EDA, is working with enthusiastic college students and open-source developers and seeing how our technology…
PicoRio: the Raspberry Pi-like Small-Board Computer for RISC-VBy Zhangxi Tan, Lin Zhang, Yi Li, and David Patterson of the RISC-V International Open Source Laboratory Tsinghua-Berkeley Shenzhen Institute RISC-V, the royalty-free open-source alternative…
Hardware Description Language Chisel & Diplomacy Deeper diveAre you using Chisel? A hardware building language based on Scala. Not a high-level synthesis language. SiFive's RISC-V IP use Chisel Rocket-Chip : https://github.com/chipsalliance/rocket-chip BOOM : https://github.com/riscv-boom/riscv-boom…
Where to start with RISC-VOriginally posted on Medium How to get started, where to contribute, and what to do next RISC-V made the news recently when BeagleBoard.org revealed the…
Overview of Diplomacy for writing effective hardware design language Chisel (Japanese)ハードウェア記述言語Chiselをもっともっと活用するためのDiplomacy概説 発表者：msyksphinz (FPGA開発日記著者) @msyksphinz_dev https://msyksphinz.hatenablog.com Chisel使ってますか？ Scalaをベースとしたハードウェア構築言語. 高位合成言語ではない SiFiveのRISC-V IPで採用されている Rocket-Chip : https://github.com/chipsalliance/rocket-chip BOOM : https://github.com/riscv-boom/riscv-boom Chiselの基礎 : 「Chiselを始めたい人に読んで欲しい本」 https://nextpublishing.jp/book/12162.html ChiselがVerilogを生成するまで ChiselはScalaのDSLなので、Chisel CompilerはScalaで記述してある Chisel CompilerはFIR (Flexible Interpretation Representation)と呼ばれる中間言語を生成する…
RISC-V CPU Performance | Maven SiliconThis video explains how Maven Silicon measures the CPU performance and how we try to improve the processor performance by improving its clock frequency and…
Let’s Make RISC-V Connected Systems Synonymous with SecurityThis blog was submitted by Silex Insight. If you are designing systems based on a RISC-V architecture, for example to run highly connected applications,…
RISC-V Microarchitecture for Kids??!! | Steve Hoover, Redwood EDALast month I had the great pleasure of sharing a blog post about Nicholas Sharkey, an amazing 13 year-old who participated with graduate students and…
What is Processor Core Complexity?This blog was originally published on the Codasip blog. The more complex a processor core, the larger the area and power consumption. But increasing…
What is Needed to Support an Operating System?This blog was originally published on the Codasip blog. For each embedded product, software developers need to consider whether they need an operating system;…
Understanding the Performance of Processor IP CoresThis blog was originally published on the Codasip blog. Looking at any processor IP, you will find that their vendors emphasise PPA (performance, power…
RPC DRAM support in open source DRAM controllerOriginal content published October 28, 2020 on the Antmicro blog. The Internet of Things is one of the areas that is hugely benefiting from miniaturization…
13-Year-Old, Nicholas Sharkey, Creates a RISC-V CoreOne of my great pleasures operating my EDA startup, Redwood EDA, is working with enthusiastic college students and open-source developers and seeing how our technology…
PicoRio: the Raspberry Pi-like Small-Board Computer for RISC-VBy Zhangxi Tan, Lin Zhang, Yi Li, and David Patterson of the RISC-V International Open Source Laboratory Tsinghua-Berkeley Shenzhen Institute RISC-V, the royalty-free open-source alternative…