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The latest from RISC-V International and community members.

SUBMIT BLOG POST
When 32 bits isn't enough — Porting Zephyr to RISCV64

Conventional wisdom says you should normally apply small microcontrollers to dedicated applications with constrained resources. 8-bit microcontrollers with a few kilobytes of memory are still…

RISC-V Global Forum – It's a wrap!

RISC-V Global Forum 2020, our first virtual event that spanned 18 hours! To find session presentations, go to the schedule of the session. If the…

RISC-V Global Forum: Initiate. Innovate. Impact.

Click to register.   There is an increase in demand for processors that will address concerns related to security, graphics, high-performance computing, and artificial intelligence.…

OpenHW open source CORE-V processor IP: a RISC-V story that leads with verification

Fig. 1. OpenHW: CORE-V processor features for CVE4 & CVA6 To help and support SoC design teams looking to adopt CORE-V, the OpenHW Group has…

Unlocking JavaScript: V8-RISCV Open Sourced

Why V8 While the software ecosystem of RISC-V has evolved rapidly in the last decade, an important domain of applications, web applications, is still missing…

RISC-V Training Partners Bring professional learning to the worldwide community!

When we think of learning at RISC-V International, it's a passion and drive to provide opportunities to the community to have access to the materials…

Welcoming RISC-V International Board Members

RISC-V International Welcomes New Board Members: Leading Growth Through Technology, Opportunity, and Community By Calista Redmond, August 3, 2020 The RISC-V community has grown and…

RISC-V Global Forum: Technology. Opportunity. Community.

The schedule for RISC-V Global Forum is live! We have an exciting lineup of keynotes, session presentations, lightning talks, ask the experts, sponsor exhibits, and…

seL4 is verified on RISC-V!

The most exciting aspect of an open ISA with open-source hardware implementations is the prospect of verifying the implementations. This sounds like a big ask…

When 32 bits isn't enough — Porting Zephyr to RISCV64

Conventional wisdom says you should normally apply small microcontrollers to dedicated applications with constrained resources. 8-bit microcontrollers with a few kilobytes of memory are still…

RISC-V Global Forum – It's a wrap!

RISC-V Global Forum 2020, our first virtual event that spanned 18 hours! To find session presentations, go to the schedule of the session. If the…

RISC-V Global Forum: Initiate. Innovate. Impact.

Click to register.   There is an increase in demand for processors that will address concerns related to security, graphics, high-performance computing, and artificial intelligence.…

OpenHW open source CORE-V processor IP: a RISC-V story that leads with verification

Fig. 1. OpenHW: CORE-V processor features for CVE4 & CVA6 To help and support SoC design teams looking to adopt CORE-V, the OpenHW Group has…

Unlocking JavaScript: V8-RISCV Open Sourced

Why V8 While the software ecosystem of RISC-V has evolved rapidly in the last decade, an important domain of applications, web applications, is still missing…

RISC-V Training Partners Bring professional learning to the worldwide community!

When we think of learning at RISC-V International, it's a passion and drive to provide opportunities to the community to have access to the materials…

Welcoming RISC-V International Board Members

RISC-V International Welcomes New Board Members: Leading Growth Through Technology, Opportunity, and Community By Calista Redmond, August 3, 2020 The RISC-V community has grown and…

RISC-V Global Forum: Technology. Opportunity. Community.

The schedule for RISC-V Global Forum is live! We have an exciting lineup of keynotes, session presentations, lightning talks, ask the experts, sponsor exhibits, and…

seL4 is verified on RISC-V!

The most exciting aspect of an open ISA with open-source hardware implementations is the prospect of verifying the implementations. This sounds like a big ask…