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Integration Challenges in RISC-V System Prototyping: The RISER Microserver Platform

By August 25, 2026No Comments3 min read

Project Snapshot

This blog post reports on the experiences and roadmap of the RISER project, which since January 2023 has been developing first-generation all-European RISC-V cloud server and accelerator prototypes capable of running fully-featured Linux-based software stacks. Building on processor IP from the EPI and EUPILOT projects, RISER targets Europe’s open strategic autonomy in cloud infrastructure. We present the RISER Microserver Platform, an FPGA-assisted prototype that integrates the EPAC1.5 RISC-V vector-processor test-chip in a standalone computing node with its own boot firmware, NVMe storage, and 100 Gbps Ethernet connectivity, and discuss the integration challenges encountered during bring-up and initial validation of use-cases.

 

Note: Project concept and results reported on behalf of the RISER project consortium. The RISER project is funded under the Horizon Europe proposal call on “Digital and emerging technologies for competitiveness and fit for the green deal”, under Grant Agreement: 101092993 (managed by HaDEA, the European Health and Digital Executive Agency).

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Meet the Author

Dr. Manolis Marazakis

Staff research scientist in Computer Science at  FORTH (Foundation for Research and Technology – Hellas) in Greece

Dr. Manolis Marazakis (Ph.D. in Computer Science, University of Crete, Greece – 2000) is a Principal Staff Research Scientist at the Institute of Computer science, FORTH. His research interests are in system architecture and efficient systems software, mainly resource management and storage I/O middleware, for high-performance servers in data center environments. He has contributed to the design, implementation and performance analysis of several system prototypes for HPC, data analytics, multi-tenant workloads, and the convergence of HPC and Cloud infrastructures. He has been FORTH’s technical lead for system software and performance evaluation for European digital sovereignty-focused research and innovation projects, for both HPC and Cloud infrastructure technologies. He is a Senior Member of ACM (since 2018) and IEEE (since 2021), and a Member of the USENIX Technical Society.