First RISC-V Foundation workshop outside North America sells out
The 6th RISC-V Workshop, co-hosted by NVIDIA and the Shanghai Jiao Tong University (SJTU) was held in Shanghai China on May 8-11, 2017. This was our first RISC-V Foundation workshop held outside of North America and as with past workshops, this event was sold out with over 270 registered attendees. Workshop proceedings are available on the riscv.org site.
Maker Faire panel talks DiY chip making with RISC-V
Dave Patterson moderated a panel, entitled “Manufacturing Your Own Chips: Is Open Source (like RISC-V) Making it Easier?”, at Maker Faire Bay Area on May 20, 2017. Among the panelists were Ted Speers, board member, RISC-V foundation, Microsemi and Jack Kang (VP Product/BD, SiFive).
GCC 7.1 Released with RISC-V Support
The GNU Compiler Collection Team released GCC 7.1 on May 2nd, 2017. In addition to a host of other improvements, this release contains support for the current RISC-V ISA specifications, including the 2.1 user ISA and the 1.10 draft privileged ISA. I’d like to thank all the RISC-V GCC contributors, but I’d specifically like to thank Andrew Waterman and Kito Cheng, my co-maintainers for the RISC-V port.
Now that binutils and GCC have upstream releases with RISC-V support the last remaining hurdle before beginning the RISC-V distribution porting effort is to get our C libraries upstream. We’re hoping to have both glibc and newlib patches submitted in the coming month, and if everything goes smoothly we hope to be in the upcoming glibc release which should be around August.
The official release message from the GCC mailing list is available here https://gcc.gnu.org/ml/gcc/2017-05/msg00017.html.
Thanks to everyone who has helped with the RISC-V software effort over the last few years. All our hard work is starting to pay off!
Interest in the RISC-V ISA continues to grow with a total membership in the RISC-V Foundation of over 75 members, research labs and universities including several new member organizations that have joined the Foundation over the past few months such as: Andes Technology, CSEM, C-Sky, Dover Microsystems, Imperas, Lawrence Berkeley National Laboratory, MediaTek, NUDT China, Princeton University, Samsung, SecureRF, Segger, Ubilite, VeriSilicon and Xtreme EDA.
Krste Asanović, Chairman of the RISC-V Foundation, writes about how Princeton’s memory model research improves the open RISC-V ISA
Rick O’Connor, Executive Director of the RISC-V Foundation, was an invited guest on the Embedded Computing Design Podcast
Microsemi releases SoftConsole 5.1, the first Eclipse based Windows IDE for RISC-V
SiFive Launches CPU IP Industry into the Cloud with New RISC-V Cores and an Easy Online Business Mode
Andes Technology Corporation the First Mainstream CPU IP Provider to Adopt RISC-V Expands Product Lineup to offer 64 bit Processor IP
Syntacore announces availability of the open-source RISC-V core
SiFive Unveils the first RISC-V-based Arduino Board at Maker Faire Bay Area
UltraSoC announces industry’s first processor trace support for RISC-V
FPGA Kongress, 11th – 13th July 2017 at the NH Hotel München-Dornach, Germany The Case for implementing a soft RISC-V core in FPGA
RISC-V at HotChips, Cupertino, California, Sunday-Tuesday, August 20-22, 2017
RISC-V at the Linley Processor Conference, Santa Clara, CA, October 4 – 5, 2017
First Workshop on Computer Architecture Research with RISC-V (CARRV 2017), Boston, MA, October 14, 2017, Co-located with MICRO 2017
Call for Papers now open for the 7th RISC-V Workshop, hosted by Western Digital in Milpitas CA November 28-30, 2017