RISC-V Workshop in Barcelona – Call for Papers

Call for Papers  RISC-V Workshop in Barcelona May 7-10, 2018 Co-Hosted By         Co-Sponsored By   We’re seeking proposals for talks and poster presentations conveying recent activity in the RISC-V community at the upcoming RISC-V workshop co-hosted by Barcelona Supercomputing Center (BSC) and Universitat Politècnica de Catalunya (UPC) and sponsored by NXP and Western Digital in Barcelona, Spain from May 7-10, 2018.Talks can be of two lengths (25 minutes and…

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Building a More Secure World with the RISC-V ISA

Krste Asanović, Chairman, RISC-V Foundation Rick O’Connor, Executive Director, RISC-V FoundationRecent articles in the media have raised awareness around the processor security vulnerabilities named Meltdown and Spectre. These vulnerabilities are particularly troubling as they are not due to a bug in a particular processor implementation, but are a consequence of the widespread technique of speculative execution. Many generations of processors with different ISAs and from several different manufacturers are susceptible…

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7th RISC-V Workshop Proceedings

7th RISC-V Workshop Proceedings November 28-30, 2017Our goals for these events are to bring the RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe, and build consensus on the future evolution of the instruction set. Tuesday and Wednesday November 28-29, 2017 – These two days followed our traditional two day format used at previous workshops with presentations covering various RISC-V projects…

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7th RISC-V Workshop Agenda

7th RISC-V Workshop Agenda November 28-30, 2017Our final agenda is posted below and registration for the 7th RISC-V Workshop, hosted by Western Digital in Milpitas California on November 28-30, 2017 is now closed as the workshop is now sold out.Our goals for these events are to bring the RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe, and build consensus on the…

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7th RISC-V Workshop Registration

7th RISC-V Workshop November 28-30, 2017Registration for the 7th RISC-V Workshop, hosted by Western Digital in Milpitas California on November 28-30, 2017 is now open.  As with past workshops, our goals for these events are to bring the RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe, and build consensus on the future evolution of the instruction set. This will be…

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RISC-V E-Newsletter June 2017

Click HERE to Join the RISC-V Foundation Mail Lists First RISC-V Foundation workshop outside North America sells out The 6th RISC-V Workshop, co-hosted by NVIDIA and the Shanghai Jiao Tong University (SJTU) was held in Shanghai China on May 8-11, 2017.  This was our first RISC-V Foundation workshop held outside of North America and as with past workshops, this event was sold out with over 270 registered attendees. Workshop proceedings are…

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7th RISC-V Workshop Save the Date

7th RISC-V Workshop November 28-30, 2017 Please save the date and plan to join us for our 7th RISC-V Workshop, hosted by Western Digital in Milpitas California November 28-30, 2017.  As with past workshops, our goals for these events are to bring the RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe, and build consensus on the future evolution of the instruction set.Each of our past…

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6th RISC-V Workshop Agenda

6th RISC-V Workshop Agenda May 8-11, 2017The preliminary agenda for the 6th RISC-V Workshop, co-hosted by NVIDIA and the Shanghai Jiao Tong University (SJTU) in Shanghai China on May 8-11, 2017 is shown below.  As with past workshops, our goals for these events are to bring the RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe, and build consensus on the future evolution of…

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The RISC-V Memory Consistency Model

Krste Asanović, Chairman, RISC-V FoundationMemory consistency models (MCMs) are known to flummox even experienced computer architects, so it is perhaps not surprising that recent news articles had some difficulty portraying the nuances behind recent findings by a team of Princeton researchers led by Professor Margaret Martonosi.  The RISC-V Foundation is publishing this article to help the RISC-V community understand the deeper implications of the Princeton study. Executive Summary The Princeton team…

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RISC-V Enters Mainstream at Embedded World 2017

Berkeley, California – Over the last year the RISC-V architecture has evolved from an academic research interest to a mainstream embedded processor technology with a rich ecosystem and a fast-growing number of real-world implementations. As a sign of this progress, a number of companies will be demonstrating commercial implementations of RISC-V products next week at Embedded World 2017, the leading international trade fair for embedded systems (March 14-16, Nuremberg, Germany) https://www.embedded-world.de/enRISC-V…

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