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Recap Of The Third Bay Area RISC-V Meetup At Rambus

By September 26, 2018October 1st, 2020No Comments

On Sept. 13, Rambus hosted the third Bay Area RISC-V Meetup at the company’s campus near Moffett field. There was a great view from the seventh floor where the meeting was held. Western Digital and SiFive had hosted the previous two Meetups, and it was great to see RISC-V member companies continue to support the Meetup efforts and enable discussion around RISC-V. There were approximately 120 people who attended the Meetup.  Notable speakers included Ted Speers of Microsemi (now a Microchip company), who provided a brief overview of the RISC-V Foundation; Palmer Dabbelt of SiFive who discussed the state of the software surrounding RISC-V; Jason Oberg of Tortuga Logic who presented on security verification; Tyler Baker from who shared an over-the-air update of a FPGA and successfully demonstrated a remote chip; and finally, Martin Scott, CTO of Rambus, who  shared more on security and the role of RISC-V in Rambus’ security efforts. All of the speakers participated in a panel discussion led by Ed Sperling, which was informative and presented a view of the industry as a whole in addition to that of each company’s.

Figure 1: Palmer Dabbelt of SiFive presenting on the state of RISC-V software

Figure 2: Palmer giving his presentation to a nearly full house
Some key quotes from attendees include Mikhail Popov, member of the RISC-V Meetup group, who said, “The meetup was great in all parts: People, agenda, speakers, and the panel! The hosting by Rambus was awesome. Thanks to the organizers.” John Cox, a semiconductor professional, added, “This meetup is and should be a model for quality meetups. It was well organized, had great speakers with relevant topics, was on-schedule, well-attended and managed by great hosts. Hats off to Mike Noonan and the entire Rambus team. Thank you and well done!”
I was interested to see just how the RISC-V ISA has been accepted and promoted by the companies looking to solve security-related issues, which was one of the main themes of the night. The RISC-V ISA does not carry any baggage. It is totally new, no backward compatibility required, which gives architects a blank page to work from. I see how this appeals to those concerned with security, being able to learn from past mistakes and implement a new core design from the ground up creates a unique solution for the semiconductor market. During the panel, security through diversity was a topic of discussion, which, to me, was a great way to talk about how effective a new approach can be to solve this problem that has impacted nearly everyone with a device connected to the Internet, or protect our personal data stored in various data centers. The RISC-V ISA is not a core design; it is the language used to execute commands. I see this as another way to create diversity. Companies that design a core based on RISC-V will each implement the microarchitecture in a different way, meaning that vulnerabilities will need to be discovered for each core design, unlike other CPU designs that have vulnerabilities that can carry over from generation to generation. I also liked the discussion about biological diversity and how nature and evolution has created living organisms that are not all vulnerable to the same virus and bug. The RISC-V ISA provides a similar diversity to core security, which gives me comfort in knowing that we can find ways to keep ahead of those attempting to hack our systems and create disruptions to society.
Overall I walked out of the Meetup feeling good about RISC-V efforts and that technologies impact on humanity will be positive in the long run, even if we only hear about security breaches in the media.
More details on the RISC-V Meetups can be found online here.

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