Last week the global RISC-V ecosystem gathered for the second annual RISC-V Summit, the biggest RISC-V event of the year. At the 2019 RISC-V Summit there were more than 1670 registrants – that’s 500 more attendees compared to the event last year, showing how the RISC-V ecosystem is continuing to rapidly grow. There were more than 40 companies with booths in the exhibit hall, plus an extra 10 companies with pods, demoing the latest RISC-V solutions. We were also proud to showcase 24 posters about RISC-V projects and implementations.
Companies issued more than 25 announcements around the RISC-V Summit, highlighting new silicon solutions, partnerships, design wins and more. Read on to find out more about what’s new in the RISC-V ecosystem and what happened at the RISC-V Summit. Also, stay tuned for videos of the sessions!
Recaps of the RISC-V Summit
- Semiconductor Engineering: Will Open-Source Processors Cause a Verification Shift?
- Tech Design Forum: Support for RISC-V Expands at Summit
- The Register: RISC-V Xmas Gifts: SiFive Emits Vector-Enabled Cores, Western Digital Teases New SweRVs, VxWorks Hugs ISA, Samsung Rolls It Into 5G
- VentureBeat: RISC-V Grows Globally As An Alternative To Arm And Its License Fees
Check out OneSpin’s series of videos with: Calista Redmond at the RISC-V Foundation; McKenzie Ross and Brett Cline at OneSpin; Rick O’Connor at the OpenHW Group; Rob Oshana at NXP Semiconductors; Sven Beyer at OneSpin; Swamy Irrinki at SiFive; Ted Marena at Western Digital; and Tim Morin at Microchip Technology.
Check out news from the Foundation’s Platinum members:
- Andes 45-Series Expands RISC-V High-End Processors 8-Stage Superscalar Processor Balances High Performance, Power Efficiency, and Real-time Determinism with Rich RISC-V Ecosystem
- Andes Corvette-F1 N25 Platform Becomes One of the First RISC-V Platforms Qualified for Amazon FreeRTOS
- Andes Presents Ground-Breaking 27-Series Processor at RISC-V Summit 2019
- Antmicro and zGlue Release Rapid Turnaround Chiplet-Based GEM ASIC
- Tensorflow Lite in Zephyr on LiteX/VexRiscv
- Microchip Unveils Family Details and Opens Early Access Program for RISC-V Enabled Low-Power PolarFire SoC FPGA Family
- Samsung To Use SiFive RISC-V Cores For SoCs, Automotive, 5G Applications by Anton Shilov, AnandTech
- Driving to Data-Centric Architectures and 1B RISC-V Cores
- Western Digital Brings Memory Closer to Compute With New RISC-V Innovations and Strategic Partnerships
Read more news from the RISC-V ecosystem:
Breker Verification Systems
- Breker Verification Systems Launches Unique RISC-V TrekApp for Automated, High-Coverage System Integration Test Suite Synthesis
- Andes Technology and Deeplite, Inc. Join Forces to Deploy Highly Compact Deep Learning Models Into Daily Life
- GreenWaves Unveils Groundbreaking Ultra-Low Power GAP9 IoT Application Processor for the Next Wave of Intelligence at the Very Edge
Hex Five Security
- Hex Five Announces General Availability of MultiZone™ Security for Linux – The First Commercial Enclave for RISC-V Processors
- Andes Certifies Imperas Models and Simulator as Reference for New Andes RISC-V Vectors Core with Lead Customers and Partners
- Lattice and SiFive Announce Collaboration to Allow Lattice FPGA Developers Easy Access to RISC-V Processors
- OpenHW Group Announces CORE-V Chassis SoC Project and Issues Industry Call for Participation
- OpenHW Group to Showcase Member Projects Based on CV32E and CV64A Open Source Cores at the RISC-V Summit 2020
- RISC-V Summit: Silicon Labs Q&A On IoT Hardware by Brian Buntz, IoT World Today
- Think Silicon® Demonstrates Early Preview of Industry’s first RISC-V ISA Based 3D GPU at the RISC-V Summit
- Veridify Security to Demonstrate DOME™ a Zero-Touch Onboarding and Device Management Solution for RISC-V Processors