The RISC-V Forums, hosted by RISC-V International, are short-form, single-topic, deep-dive virtual events. This is the spirit of RISC-V events – providing technical content to the RISC-V community for free!
If you joined us for our forum on Security, you were one of 700 (!) people that registered for the event and maybe one of the nearly 2,000 (!!) people that watched the content on our YouTube channel. It’s wonderful to see so much interest!
The schedule for the Developer Tools and Tool Chains Forum is live and it’s amazing! Join us on June 2 from 7:00 a.m. to 10:15 a.m. PT (4:00 p.m. to 7:15 p.m. CEST).
The tool chain and run-time horizontal committee is responsible for all parts of the compiler and profilers such as GCC, LLVM, Valgrind, GDB (debugger), ld (linker), and many others. Join this event for the latest in RISC-V tool chains.
Live Q&A! Many sessions will have time for attendees to ask questions.
Join us for the RISC-V Developer Tools and Tool Chains Forum on June 2!
Look at this amazing content! You can see the full schedule here.
- RISC-V Tools & Runtime HSC Overview – Christoph Müllner, SBA Research & Philipp Tomsich, VRULL GmbH. Hear what is going on with the Tools and Runtime horizontal committee.
- Java on RISC-V: OpenJDK Porting Work Update – Sanhong Li & Kevin Kuai, Alibaba Cloud. In this talk, you’ll learn about the current status of port development on OpenJDK for RISC-V architecture, and the compatibility and performance issues while running the full Java application on RISC-V with OpenJDK
- Analysis for Code Size Opportunities in RISC V – Ibrahim Abu Kharmeh, Huawei UK. Ibrahim will shortly go over why code size density is important, introduce the Zce extension and its main proposed instructions.
- Programmer Productivity and Performance on Embedded RISC-V CPUs – Nick Brown, EPCC at the University of Edinburgh. In this talk, Nick will provide a brief overview of ePython for RISC-V, describe how the internals support such constrained architectures, and share our roadmap for productionisation of this open-source technology.
- CFU Playground: Model-specific Acceleration on FPGAs – Timothy Callahan & Alan V. Green, Google. This talk describes the CFU Playground, an open source framework that an engineer, intern, or student can use to design and evaluate enhancements to an FPGA-based soft RISC-V processor, specifically to increase the performance of machine learning (ML) tasks through the addition of custom function units (CFUs).
- Linker Relaxation in LLD – Chih-Mao Chen, Andes Technology. This talk will provide a brief overview on how linker relaxation works in RISC-V, describe our relaxation implementation and alignment handling in LLD, and present benchmarking results after enabling relaxation.
- Exploring Static Code Generation and SIMD-Acceleration for Machine Learning on RISC-V – Rafael Stahl, Technical University of Munich. In this talk, two static code generators based on TensorFlow Lite for Microcontrollers and TVM are presented that avoid these overheads by generating static code to execute the model