By: Putta Satish, Principal Engineer, Maven Silicon
In this demo video, Putta Satish explains the complete RISC-V DV flow: RISC-V RTL pipeline architecture overview, RISC-V processor verification plan, UVM TB architecture, test cases, Regression Testing, and Verification sign-off with coverage
Satish has created and presented this RISC-V Design Verification demo video for the VLSI Design Conference 2023 RISC-V Tutorial.
Follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats, RTL Architecture, etc. To know more, explore our RISC-V courses.