Antmicro, our Mi-V ecosystem partner, has been cooperating with Microchip for many years now, enabling our Mi-V ecosystem with its simulation solutions. Both companies are founding members of RISC-V International and have been driving the RISC-V free and open Instruction Set Architecture (ISA) ecosystem since the early days.
Since the beginning of this ongoing collaboration, we have been working hand in hand, providing a complete Renode-based simulation platform for the Mi-V ecosystem, including both Mi-V soft central processing units (CPUs) and the highly advanced multi-core PolarFire® System-on-Chip Field-Programmable Gate Array (SoC FPGA), capable of co-simulation enabling rapid co-development of software and FPGA code.
Renode – Antmicro’s advanced simulation framework
Renode is Antmicro’s open-source simulator capable of accelerating any development stage of Internet of Things (IoT) and embedded systems. It allows you to build virtual SoCs using a wide range of peripherals and CPUs of various architectures, like ARM or RISC-V. Renode offers a wide range of features, including co-simulation between fast models of your core system—such as the hard blocks of Microchip PolarFire SoC FPGA and a specific peripheral or subsystem—e.g. developed in your PolarFire SoC FPGA fabric—directly from HDL. This significantly speeds up your system development in complex scenarios, as functional simulations are noticeably faster than HDL simulations.
Thanks to Renode’s advanced debugging and testing capabilities, you can catch bugs earlier in the development cycle and get greater control over your target platform and its environment. Renode can also be used during the pre-silicon stage of a project, as has been done by Microchip to enable software development for their PolarFire SoC FPGA before it was physically built and distributed.
PolarFire SoC and Icicle in Renode
The collaboration of Antmicro and Microchip helped to reach a significant milestone in Renode’s history. You can find the GitHub repository for the development of a 64-bit multicore PolarFire SoC here. The FPGA SoC is equipped with a 5-core Linux-capable processor subsystem based on the RISC-V ISA. Its simulation in Renode supports a wide range of peripherals, starting with low-speed communication interfaces like SPI, through USB and PCIe support, to hardware-accelerated cryptography. Additionally, as mentioned before, users can benefit from Renode’s co-simulation capabilities, allowing them to use their Verilog code as simulation models within the Renode environment.
Microchip also provides a low-cost development platform—the Icicle Kit, which is supported in Renode as well. You can easily run it using only one command in the Renode CLI:
“`
start @scripts/single-node/icicle-kit.resc
“`
This simulation runs Yocto-based Linux with a full bootloader flow to be as close to the physical hardware experience as possible.
Integration with Microchip SoftConsole
Microchip provides an Eclipse-based Integrated Development Environment (IDE) for developing bare metal- and real-time operating system (RTOS)-based C/C++ software, named Microchip SoftConsole, which has been integrated with Renode as part of our cooperation. This integration is based on GDB support in Renode and as a result, Renode now ships as an integrated part of SoftConsole. This allows you to start the debugging of your system with just a single click, both on Mi-V soft CPU cores and the PolarFire SoC FPGA. This pairing is especially effective considering Renode lets you run the same unmodified binaries you would use on the target hardware.