Top Ten Fallacies About RISC-V

David Patterson, Pardee Professor of Computer Science, Emeritus at UC Berkeley

and Vice Chair of the RISC-V International Board of Directors

Following the Fallacies and Pitfalls section in every chapter of Computer Architecture: A Quantitative Approach, this paper gives ten fallacies about RISC-V today (below). We next explain the flaws of these fallacies.

1. RISC-V is an open-source processor, like Linux is an open-source operating system.
2.  All RISC Instruction Set Architectures (ISAs) are equivalent.
3.  Picking an established, closed ISA is a safer business decision than picking the new open RISC-V.
4. RISC-V ISA is only gaining popularity because it’s cheaper.
5.  Closed ISAs do not have fragmented software ecosystems.
6. RISC-V modularity leads to a more fragmented software ecosystem than those of closed ISAs.
7.  RISC-V is only good for embedded applications.
8.  RISC-V is not as secure as a closed ISA.
9. RISC-V processors will always trail the more established closed processors in high performance and robustness of the software ecosystem.
10. Given the points above, RISC-V cannot become the dominant ISA.

1. Fallacy: RISC-V is an open-source processor, like Linux is an open-source operating system.

Linux has a single master open-source code base you can download, while RISC-V is an open specification of the hardware/software interface for which there are many different implementations. A better analogy than Linux is Ethernet, since both Ethernet and RISC-V are free and open specifications. 

Before the Ethernet standard, companies had their own proprietary local area networks (LANs): Apple AppleTalk (1985), Datapoint ARCNET (1977), Digital Equipment Corporation DECnet (1975), IBM Token Ring (1984), Xerox Ethernet (1974), and so on. In 1980 Digital Equipment Corporation, Intel, and Xerox (“DIX”) joined forces to create a local network standard based on Ethernet. They also created an organization—IEEE 802.3 working group—that has advanced the Ethernet standard over the past four decades. 

Ethernet made rapid advances in cost and performance because many companies could build network products that ran the same software stack on top of the Ethernet standard. While you can design your own Ethernet switches and there could be open hardware designs to download, many simply buy switches that meet the Ethernet standard. A decade after the creation of the “DIX” standard, Ethernet became the dominant networking technology. Today, proprietary LANs are practically extinct. Does anyone miss them?

The popular Universal Serial Bus (USB) also followed the Ethernet game plan by providing a free and open standard for peripheral interconnect that is embraced by many companies plus an organization to evolve it.

Like Ethernet and USB, RISC-V is an open standard that lets many organizations design hardware, which fosters competition to improve its cost-performance and develop a rich shared software ecosystem that offers RISC-V products in many markets. Like Ethernet and USB, RISC-V also has a foundation that evolves the standard over time to meet new demands. Like Ethernet and USB, you can buy RISC-V hardware, build it yourself, license designs, or download open-source designs.

2. Fallacy: All RISC Instruction Set Architectures (ISAs) are equivalent.

While RISC architectures share some characteristics, RISC-V has unique features compared to previous ISAs, in part because it is newer and in part because of the philosophy of its architects. These features led the EU to pick RISC-V for its processor initiative and NASA to pick RISC-V for future space missions.

RISC-V has a small core set of instructions that all software runs on, plus optional extensions that processor designers and compilers can choose to use. Thus, RISC-V designs can be smaller and use less energy as they can omit features when they are unnecessary. Profiles provide standard targets for particular segments (see Fallacy 7).

RISC-V also provides a few features not found in another popular RISC ISA, the ARMv8 and its successors: 

• RISC-V supports the addition of custom instructions to accelerate an application. Examples are applications for machine learning or for digital signal processing.
• RISC-V offers compact instructions that reduce code size. The same-sized instruction cache can store ~50% more RISC-V instructions, which reduces cache misses and therefore clocks per instruction (CPI).
• RISC-V has a single compare and branch instruction vs two instructions (set condition codes, then branch on them). Conditional branches are 10%-20% of instructions executed, so the savings are significant. 

3. Fallacy: Picking an established, closed ISA is a safer business decision than picking the open RISC-V. 

It’s easy to forget that a closed ISA is tied to the success of the company that owns them, and it can disappear if the company falters. For example, the once-popular DEC VAX, DEC Alpha, and Sun SPARC ISAs are extinct. 

It’s also hard to remember that closed ISAs are intellectual property that can be sold to companies with different goals than its predecessors. For example, the MIPS ISA has had more than a half-dozen owners, and so far the Arm ISA has had three: Acorn, ARM Holdings plc, and Softbank. By comparison, RISC-V is driven by the collective participation of hundreds of companies in a neutral open standard organization, RISC-V Inter- national. Their collective interests determine the evolution of RISC-V through this non-profit foundation.

Like Ethernet and USB, RISC-V is not tied to the fortunes of any one company, so it is a more prudent bet for a company’s software ecosystem development for the long haul. This long-term safety is another reason the EU and NASA picked RISC-V for their future plans.

 4. Fallacy: The RISC-V ISA is only gaining popularity because it’s cheaper. 

First, there are other reasons besides being cheaper to explain RISC-V’s popularity. Fallacies 2 and 3 above point out the advantages of RISC-V independent of cost. Beyond the advantages in the ISA itself, being an open standard means more organizations will be designing hardware for the open specification than for any other (like Ethernet or USB), which should lead to better versions of RISC-V cores than cores designed by a handful of organizations. Thus, the ISA’s advantages and the larger developer community likely means better performance- power-area for RISC-V processors than for conventional ISAs. Finally, like Ethernet or USB, the many suppliers of RISC-V mean one can start a project before signing a contract or NDA, which can take months to negotiate. Thus, picking RISC-V (or Ethernet or USB) could save development time even if there was no cost benefit. 

If you want to design your own hardware, RISC-V is indeed cheaper since the specification is free and open; there is no architecture license fee, which can cost tens of millions of dollars for closed specifications. Since the spec is open, there are also free open source examples you can download, use, and modify, which is not an option for closed ISAs. If licensing a design, the open specification means you have your choice of multiple commercial vendors and implementations. Compared to single source designs, competition generally reduces prices.

 While there may be cost advantages, RISC-V is gaining popularity primarily because of the design freedom inherent in its business and technical model. This benefit ensures that stakeholders can rapidly create competitive solutions using resources from a variety of mutually invested partners while avoiding vendor lock-in.

5. Fallacy: Closed ISAs do not have fragmented software ecosystems.

Older closed ISAs have suffered from unforeseen incompatibilities over their long lifetimes. Here are a few examples:

• Despite trying to share the x86-64 ISA, AMD and Intel require different virtual machines.
• Intel AVX-512 is significantly fragmented.
• ARM compilers use many runtime tests to see if SIMD features are available before using them.
• ARM1 to ARMv7 use a 32-bit address space but they are incompatible with ARMv8-A and successors, which offer both 32- and 64-bit address versions. ARMv8-M adds new features to the older 32-bit ISA, but is incompatible with ARMv8-A.

No software environment is more fragmented than today’s system on a chip (SOC) for edge devices. They include many incompatible ISAs and software stacks for the many types and brands of processors (application CPUs, embedded CPUs, DSPs, ML accelerators and ISPs). One reason is because these processors use closed ISAs that cannot be used for third party IP, so each processor block has its own ISA. 

6. Fallacy: RISC-V’s modularity leads to a more fragmented software ecosystem than those of closed ISAs.

This fallacy has been raised since we first started advocating for RISC-V, so it’s not been neglected. Some market segments require a stable ISA and even binary compatibility, which RISC-V addresses with profiles. They specify a set of ISA choices from the standard extensions that capture the most value for most users in a market, enabling the software community to focus resources on building an appropriate software ecosystem. Similarly, hardware vendors structure their offerings around standard profiles to ensure their designs will have mainstream software support. For example, RISC-V offers them for 64-bit address UNIX systems. Profiles are the foundation upon which portable apps and OSes can be built.

Beyond profiles, the RISC-V ISA offers the exciting possibility of a common base ISA with custom enhancements and a shared software stack across the many processors of an SOC. RISC-V potentially could dramatically reduce the fragmentation of today’s SOC software ecosystems (see Fallacy 5 above).

7. Fallacy: RISC-V is only good for embedded applications.

The most successful initial market for RISC-V has been embedded computers; they leverage the RISC-V modularity and customizability to improve performance-power-area, have the simplest software stack, and  have more greenfield opportunities. Even if the fallacy were true, embedded/IOT is an exciting market that enables new gadgets that we all rely upon everyday. This segment represents 90% of the processors shipped annually and has  revenues comparable to the server market. 

However, even a casual glance at RISC-V International’s membership suggests that companies are already developing RISC-V products in other markets, such as aerospace, automotive, high-performance computing, and data centers.

The history of Ethernet may be instructive about the future of RISC-V. Many networking standards have been proposed to replace Ethernet in new markets (e.g., ATM, FDDI, and Infiniband), yet Ethernet is used everywhere today, from 1 gigabit to 400 gigabit links and switches; it is the lingua franca of networking.

Similarly, RISC-V has the chance to become the lingua franca for computing, offering the same base ISA from the smallest embedded device to the largest supercomputers, plus extensions that tailor it to different markets.

8. Fallacy: RISC-V is not as secure as a closed ISA.

One advantage of an open ISA is that experts in many fields and in many organizations can participate in the design of new features before they are finalized. One of the most active committees in the RISC-V community is the security special interest group, which has been developing many security features for RISC-V, including cryptographic extensions and trusted execution environments. This progress is a reason that RISC-V is becoming popular in markets with more emphasis on security, from SOCs to disk drives, automotive, and even legacy boot cores.

9. Fallacy: RISC-V processors will always trail the more established closed processors in high performance and robustness of the software ecosystem.

The competitors to the Ethernet standard surely raised this same fallacy in the early 1980s. While the older closed ISAs have a head start, like the early days of Ethernet we believe the gap will close as more hardware and software companies realize the benefits of embracing a free and open ISA standard (see Fallacy 7). RISC-V lets companies both diversify their business interests and invest in technologies ahead of the life cycle curve. For example, MIPS now offers RISC-V designs to supplement the ISA for which it is best known. For software companies, the ability to run on different hardware platforms is an opportunity to participate in multiple markets, thus spurring investment and adoption.

In summary, it is too expensive for most companies to develop or own an architecture and ultimately have the sole responsibility for a robust software, regardless of community or dedicated third party efforts. RISC-V addresses that by the community owning this by definition, which allows companies to innovate, not duplicate.

10. Fallacy: Given the points above, RISC-V cannot become the dominant ISA.

We believe the above points are fallacies, they can’t really block the growth of RISC-V. 

There is no technical disagreement that a single base ISA could be used everywhere from embedded systems to supercomputers; the main argument is a business one, of whether it should be a closed ISA or an open ISA. If we do achieve a lingua franca for computing, it seems self-evident that it would be too dangerous for the fate of the entire information technology industry to be tied to the fortunes of a single company. It would be much safer if we could instead depend upon a free and open standard, just as we did for networking and peripheral interconnect.

In a little over a decade, RISC-V has arguably become at least the third most important ISA for future applications of computing. The enthusiasm for an open ISA that we see across the industry reminds those of us old enough to remember of the groundswell for an open networking standard in the early days of the standardization of Ethernet. In the next few years it may become just as surprising to pick a proprietary ISA over the open RISC-V for a new project as it would to pick a closed alternative to Ethernet or USB.

Just as the free and open Ethernet is the dominant network and the free and open USB is the dominant external peripheral interconnect, we predict that by the end of this decade the dominant ISA for future product development will be the free and open RISC-V.

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1. Digital, Intel and Xerox, 1980. The Ethernet, A Local Area Network. Data Link Layer and Physical Layer Specifications.
2.  While the 32-bit ARMv3 to ARMv7 ISAs offer compact instructions, the 64-bit ARMv8 and successor ISAs do not.
3.  See Processor compatibility mode in Hyper-V.
4.  The last table in the AVX-512 wikipedia page shows the haphazard use of features, e.g., Cooper Lake (2020) and Zen 4 (2022) have BFloat16 arithmetic, but not Ice Lake (2019), Tiger Lake (2020), Alder Lake (2021), or Rocket Lake (2021). 
5. Asanović and D. Patterson, August 2014. Instruction sets should be free: The case for RISC-V.
6.  RISC-V Profiles, https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc.
7.  Profiles are compatible with the inclusion of custom instructions, which are typically invoked via optimized libraries.
8. Slovick,  The Automotive Space Gears Up to Take on RISC-V, Sept. 26, 2022, Electronic Design.
9. Mann, China may prove Arm wrong about RISC-V’s role in the datacenter, Oct. 5, 2022, The Register.
10.  As long as an ISA has 32-bit address and 64-bit address versions, which RISC-V and many other ISAs offer.