By: Kezia Leung
The RISC-V Summit China 2023 is just around the corner, and during RISC-V Summit Europe Dr. Yungang Bao shared some fascinating insight on RISC-V projects taking place in China. RISC-V Summit Europe 2023 welcomed attendees from across the globe, including members of the RISC-V Community, representing diverse sectors such as industry, government, research, and academia. Together, they delved into the transformative potential of RISC-V and its impact on the future of innovation. Among the event’s highlights was Dr. Yungang Bao, a distinguished professor at the Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS) as well as the deputy director of ICT-CAS, and the founder of the China RISC-V Alliance (CRVA). His enthusiasm for RISC-V signals the emergence of an exciting new ecosystem and a thriving community in China.
The Positive Impacts of an Open Standard ISA
China’s enthusiasm for RISC-V stems from its numerous benefits as an open standard. There is a high cost of innovation in chip design, with a startup having to raise around $20 million to deliver a working prototype compared to $3 million for an internet startup. These internet startups benefit from the open source software ecosystem. According to Dr. Bao, the availability of this ecosystem allows a team of 3-5 engineers to efficiently develop and deploy an app in less than 5 months.
To bring similar benefits to the field of chip design, Dr Bao envisions an Open Source Chip Ecosystem (OSCE), to ease the barriers to chip development, with faster time to market and lower cost. With an open standard ISA, and open source IPs, SoCs, languages, EDA tools, verification, simulation environments, operating systems, and compilers, you can create a platform with 90% reusability. The new custom design will only need under 10% new lines of code. As a result, these benefits substantially lower the barriers to chip development, empowering engineers to accomplish more by leveraging shared resources.
The excitement surrounding RISC-V in China is driven by the advantages of an open standard, Dr. Bao sees RISC-V as the foundation of the Open Source Chip Ecosystem (OSCE) which empowers engineers to be more productive and fosters collaborative innovation.
The Innovative RISC-V Projects in China
China is at the forefront of embracing and innovating with RISC-V technology. RISC-V CPUs are widely adopted and the top ten RISC-V startups in China have funding totaling over $1 billion. China contributes to a wide range of RISC-V ecosystem projects, with wide support in research and education.
The China RISC-V Alliance (CRVA), was founded in 2018 and has a 3 step plan, to:
- Deliver silicon-proven open source RISC-V based IP and SoCs in 3-5 years
- Develop open source SoCs using open source EDA tools in 5–7 years
- Build open source hardware automatically using open source EDA tools in 10-15 years
The first version of the XiangShan open source high-performance RISC-V core was implemented in silicon in January 2022 and version 2 is under development with a 40% performance improvement over v1. To verify XiangShan, a new open source Agile Verification Platform was developed which enables both functional and performance verification. XiangShan is already being adopted by companies in real applications.
In 2019, Bao took the initiative to launch the One Student One Chip (OSOC) program, dedicated to teaching undergraduates how to build real chips. This visionary endeavor goes beyond the conventional textbook approach, as it embraces a “learning by doing” model, encouraging students to gain hands-on experience with actual physical chips. By adopting this contemporary learning style, students are empowered to expand their knowledge beyond the confines of traditional learning materials.
Remarkably, the initial OSOC team, comprising just 5 undergraduate students, accomplished an astounding feat by designing a 64-bit RISC-V processor capable of running Linux in a mere 4 months! This remarkable success has garnered tremendous interest, leading to the participation of over 4,000 students from more than 300 universities across China in the OSOC initiative. It is truly inspiring to witness undergraduate students taking the lead in pioneering new RISC-V projects, underscoring the pivotal role students play in shaping the future of RISC-V technology.
Furthermore, Bao pointed out that some students have taken up the task of translating the RVI certification course into Mandarin Chinese, aiming to facilitate their peers’ understanding of RISC-V in China. As more students express interest in this certification, universities across the nation can better equip their students with RISC-V skills and knowledge.
Undeniably, the future of RISC-V in China is in the hands of these passionate and driven students, who not only design their own chips but also actively contribute to their peers’ learning and engagement with RISC-V technology. Their collective efforts signal a promising future for RISC-V in China’s educational and technological landscape.
Discover the Future at RISC-V Summit China
Universities, professors, and companies in China have a lot in store for the future of RISC-V. Join in and be a part of the open standard movement, actively supporting RISC-V’s growth in China by securing your spot at the RISC-V Summit China, where you’ll gain valuable insights from prominent individuals like Dr. Yungang Bao and delve into the remarkable innovations shaping the Chinese technological landscape.