Q&A with Chris Morrison, Director of Product Marketing at Agile Analog
Tell us about Agile Analog.
At Agile Analog we are reinventing analog IP. We have developed a unique way to automatically generate analog IP that meet the customer’s exact specifications on almost any process from any foundry. Our novel digitally wrapped approach simplifies and accelerates the semiconductor design process. At RISC-V Summit Europe we launched our new analog IP subsystem for RISC-V IoT applications.
What’s the key goal for Agile Analog?
It’s all about making it easier for the digital designer to interface with the analog world. Whether it be timing, or voltage regulation, or sensing pressure or temperature, there are a myriad of things that need analog. Analog integration has always been seen as a bit scary. What we do is take our analog IP and wrap it up in digital so it looks like digital to a digital designer.
How does Agile Analog benefit the RISC-V ecosystem?
RISC-V has opened the door to enable lots of designers to create chips for the first time. We help by providing innovative analog IP in a format that’s simple for digital designers to understand and we make sure it works well when crossing from the analog to digital – we will do all the mixed signal verification and present it so it looks like a digital block to the integrator.
Collaboration is key. We are not competing against the RISC-V vendors, we are working very much with them. So, it’s possible to pick up the digital block from a company like Andes and come to us for the analog block. And then integrate the two together seamlessly into a complete block.
Why is Agile Analog so different?
Conventional off-the-shelf analog IP involves constraints, compromise, and complexity. With our unique technology we can create customizable analog IP to match a client’s own requirements. Our expanding range of analog IP products covers data conversion, power management, sensing, security, and always-on domains. Plus – with our digitally wrapped subsystems we can ensure that multiple blocks of our analog IP work well with each other and integrate easily.
We can optimize the area, because we can control the layout, and we can optimize the power, because we can put blocks that need to communicate with each other next to each other. So, from the analog side there are benefits, but even more than that on the digital side with the mixed signal boundary, where there could be clock domain crossing issues, bus domain crossing issues, and reset domain crossing issues, we can verify all of these, and then deliver a complete package.
What’s coming next?
We are committed to extending our product portfolio to make life easier for chip designers. The RISC-V community is an important focus for us.
The first Agile Analog RISC-V subsystem is predominantly for IoT and battery-powered embedded applications. It’s low power and has the features that are needed for wearables, headsets or anything that is battery-powered and portable.
Looking ahead, we plan to develop subsystems to address built-in testing, advanced power management and more sophisticated process, voltage and temperature (PVT) sensing.