By: Maven Silicon
We are delighted to inform you that we have recently published Advanced RISC-V Processor IP Design and Verification Online Courses. Our Founder and CEO, Mr. Sivakumar P R, authored these online courses for Electrical/Electronics Engineers/Graduates and experienced VLSI – Chip Designers who want to explore the RISC-V ISA and design processors and microcontrollers using it.
The RISC-V Processor is becoming very popular and influential, like the open-source operating system Linux. In this AI era, chip designers are empowered with open computing solutions like RISC-V Open ISA to design powerful AI chips using various processors and accelerators. As RISC-V Open ISA democratizes processor design, chip designers can now dream of independently creating their processors and chips with their innovations. So, it’s the right time for chip designers and VLSI enthusiasts to explore the RISC-V Open ISA and how to design a RISC-V processor.
RISC-V Processor IP Design Course: This online course will cover the RISC-V ISA, which includes Base ISAs, Privilege Architecture – Machine, Supervisor and Hypervisor ISAs/Extensions, RISC-V Standard Extensions, Interrupts, RISC-V Debug and Pipelined RTL architecture. As part of this hands-on course, you will learn Verilog HDL and create a RISC-V muti-stage pipelined processor RTL using Verilog. Also, you will verify the RISC-V RTL IP design using an existing UVM Testbench[Encrypted VIP] and synthesize it. This project experience will help you to deal with designing any complex RISC-V processors.
RISC-V Processor IP Verification Course: This online course will cover the RISC-V ISA, which includes Base ISAs, Privilege Architecture – Machine, Supervisor and Hypervisor ISAs/Extensions, RISC-V Standard Extensions, Interrupts, RISC-V Debug and Pipelined RTL architecture. As part of this hands-on course, you will learn Verification methodologies, SystemVerilog, Universal Verification Methodology [UVM], SVA, Code and functional coverage, and verify a multi-stage Pipeline Processor RTL using UVM. This project experience will help you to deal with verifying any complex RISC-V processors.
RISC-V SoC Design Course: This course will cover the RISC-V ISA, which includes Base ISAs, Privilege Architecture – Machine, Supervisor and Hypervisor ISAs/Extensions, RISC-V Standard Extensions, Interrupts, RISC-V Debug and Pipelined RTL architecture. As part of this hands-on course, you will learn SoC architecture, SoC design methodology and flow, SoC interface protocols – AMBA [AXI, AHB, APB], SPI, UART, I2C, GPIO, RISC-V IP design and verification, RISC-V SoC project implementation – RTL, Synthesis, DFT, and PD. This project experience will help you to deal with designing any complex RISC-V processors, RISC-V SoCs and Microcontrollers.
In this video, our CEO explains how he has authored these online courses and how you can upskill on the RISC-V Open ISA independently: watch the video now