Project Snapshot
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides through creating a 5-stage pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed and taught at Graz University of Technology, this resource combines hands-on exercises in hardware/software co-design with practical processor implementation on FPGAs.
In Their Own Words
Poster Preview
Meet the Authors
Dr. Tobias Scheipel
Postdoctoral Researcher at Graz University of Technology
Dr. Tobias Scheipel is a postdoctoral researcher and teacher at the Embedded Architectures & Systems Group at the Institute of Technical Informatics, Graz University of Technology. He conducted his doctoral/PhD studies under the supervision of Prof. Marcel Baunach, where he got promoted to a Doctor of Engineering Sciences (Dr.techn.) under the auspices of the Federal President of the Republic of Austria, being the highest possible distinction for academic achievements for a doctoral degree in Austria.
His research focuses on flexible and runtime-reconfigurable FPGA-based microcontroller architectures for embedded systems based on RISC-V. This involves hardware/software codesign strategies for both processor logic and embedded operating systems. Within this research area, he is the author of several peer-reviewed scientific publications in international journals and conference proceedings. He is a member of Euromicro, the Association for Computing Machinery (ACM), and the German Informatics Society (Special Interest Group Operating Systems).
Apart from research at Graz University of Technology, he teaches students how a CPU works, how to program embedded systems, how to write scientific publications, and how to create their own CPU.
David Beikircher
Master’s Student in Information and Computer Engineering at Graz University of Technology
David Beikircher is a master’s student in Information and Computer Engineering at the Graz University of Technology, focusing on embedded systems and robotics. During his studies, he successfully completed his bachelor’s degree and became part of the Embedded Architectures & Systems Group at the Institute of Technical Informatics, Graz University of Technology, where he supported teaching activities as a student assistant. His current academic focus lies in the field of FPGA design, specifically exploring placement algorithms as part of his master’s thesis.
Florian Riedl
Master’s Student in Information and Computer Engineering at Graz University of Technology
Florian Riedl is a master’s student in Information and Computer Engineering at Graz University of Technology. At the Institute of Technical Informatics he supports other students learning about digital hardware design as part of the microcontroller design laboratory in the Embedded Architectures & Systems Group. His research currently focuses on empowering hardware designers with better tooling, with a special focus on modern hardware description languages for his master’s thesis.