Opening Up New Design Possibilities with OmniXtend
I am thrilled to see the announcement and initiation of collaboration between CHIPS Alliance and RISC-V International on the OmniXtend Cache Coherency protocol.... Read more.
NASA Joins Forces with Small Business Team | Tactical Computing Labs
Proposed System Architecture Application for Space Advancement
MUENSTER, TEXAS, March 2021: NASA has selected 365 U.S. small business proposals for initial funding... Read more.
Imperas releases free ISS for RISCV-V CORE-V developers in the OpenHW ecosystem | Imperas
Imperas simulation technology with RISC-V reference models of the OpenHW CORE-V IP portfolio released as free Instruction Set Simulator for software development.
Oxford,... Read more.
Geniatech DB1126 development board features RV1126 SoC for AI applications | ABHISHEK JADHAV, CNX-Software
Since the release of Rockchip RV1126 SoC, we have covered the detailed specifications on the chip and the RV1126-based Firefly dual-lens AI camera module. To take... Read more.
Open-Source Verification not as Easy as Design | John Blyler, Design News
The allure of open-source hardware is the flexibility for designers to create their own CPU-based platforms. Advocates believe that freely available open-source... Read more.
What Does RISC-V Stand For? | Semiconductor Engineering, Roddy Urquhart
RISC-V (pronounced “risk-five”) stands for ‘reduced instruction set computer (RISC) five’. The number five refers to the number of generations of RISC architecture that... Read more.
Fun Hardware With RISC-V Processors | TWiT Tech Podcast Network
Keith Packard shares his passion of hobbyist rocketry and hardware design. Packard and his partners develop hardware for rocketry kits using RISC-V processors. Doc... Read more.
Video: Intel to Make ARM & RISC-V Chips!!! | Gary Explains
ntel made several major announcements recently including the launch of its Intel Foundry Services business. It will offer capacity in the U.S. and Europe, along... Read more.
Video: MAX30102 Pulse Oximeter and Heart Rate Sensor Demo using VEGA Processor [ RISC-V ISA]
Demonstrating MAX30102 Pulse Oximeter and Heart Rate Sensor using VEGA Microprocessor based on RISC-V ISA
Source code : https://gitlab.com/cdac-vega/ ... Read more.
RISC-V XIP Support Queued Ahead Of Linux 5.13 To “eXecute In Place” | Michael Larabel
It looks like the Linux 5.13 kernel will be supporting an interesting RISC-V feature this spring.
Queued up now in RISC-V's "for-next" branch as of this week... Read more.