RISC-V Announces Ratification of the RVA23 Profile Standard
Vector and Hypervisor extensions are key mandatory components of the RVA23 Profile, addressing math-intensive workloads including AI/ML & cryptography, and enterprise... Read more.
RISC-V Summit North America 2024: Keynotes and Industry Tracks
The RISC-V Summit North America 2024 is a pivotal event for the RISC-V community, bringing together innovators, developers, and thought leaders who are driving advancements... Read more.
Optimizing the RISC-V Backend
Hello everyone! A month and a half ago, we wrote about the latest status of the RISC-V DynaRec (Dynamic Recompiler, which is the JIT backend of Box64) and shared... Read more.
Are IoT Hardware Vendors Finally Going Open Source?
The open-source revolution is expanding beyond software into hardware design. New microcontrollers from Microchip Technology and Espressif incorporate processors... Read more.
Software-defined processors: the promise of RISC-V
It’s an exciting time to be involved in open source. Linux powers the world’s most critical devices, a story to which Red Hat has always been a champion. ... Read more.
Don’t Miss Out: RISC-V Summit North America 2024 – Register Before Prices Increase!
The RISC-V Summit North America 2024 is fast approaching, and it's a must-attend event for those interested in shaping the future RISC-V and open standards. From... Read more.
LDRA extends RISC-V support, adds QNX
LDRA has extended support for the RISC-V instruction set architecture (ISA) in its high assurance quality analysis and verification tool suite. The LDRA static... Read more.
CEO interview: Chips Act boost for RISC-V
Nick Flaherty talks to Calista Redmond, CEO of RISC-V International, on how the European Chips Act is driving the open instruction set architecture forward. “The... Read more.
Synopsys RISC-V ARC-V processor IP gets Lauterbach debug and trace
Lauterbach has extended their industry leading TRACE32® debug and trace tools to include support for Synopsys’ RISC-V instruction set based ARC-V™ processor... Read more.
Towards Generic RISC-V TEE Ecosystem with Penglai and OP-TEE
By Erhu Feng (Shanghai Jiao Tong University), Qingyu Shang (Shanghai Jiao Tong University), Yu-Chien Lin (Andes), Che-Chia Chang (Andes), Bing Gui (Nuclei) Introduction... Read more.