SME: Scalable Masking Extensions | Ben Marshall and Dan Page, University of Bristol and PQShield Ltd
Abstract: Supporting masking countermeasures for non-invasive side-channel security in instructions set architectures is a hard problem. Masked operations often... Read more.
How the Imagination RVfpga: Understanding Computer Architecture course is giving engineering under-grads real-world skills | Robert Owen, Imagination Technologies
If you were to take a look through the academic materials now available about RISC-V you will find a wealth of information around SoC creation, including inventing... Read more.
Looking Towards the Future: FreeBSD on the RISC-V Architecture | Klara
The majority of people in the tech community are well aware of the two main chip architectures: x86 and ARM. Each has its own strengths and weaknesses. Today, however,... Read more.
Pixel 6: Setting a new standard for mobile security | Dave Kleidermacher, Jesse Seed, Brandon Barbello, and Stephan Somogyi, Android, Pixel & Tensor security teams, Google Security Blog
With Pixel 6 and Pixel 6 Pro, we’re launching our most secure Pixel phone yet, with 5 years of security updates and the most layers of hardware security. These... Read more.
RISC-V-Based VEGA Brings Continual Learning to TinyML with an Order of Magnitude Efficiency Gain | Gareth Halfacree, Hackster.io
A team of computer scientists have developed a RISC-V-based platform for embedded machine learning workloads — and say it offers 65 times the performance and 37... Read more.
High-Level Synthesis For RISC-V | Brian Bailey, Semiconductor Engineering
Abstraction is the key to custom processor design and verification, but defining the right language and tool flow is a work in progress.
High-quality RISC-V implementations... Read more.
Kneron Edge AI SoC Powered by Andes RISC-V Processor Core D25F | Andes Technology
Kneron Inc., the San Diego-based Edge AI solution provider, together with Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading... Read more.
How Alibaba is Porting RISC-V to the Android OS | Guoyin Chen, Alibaba
With the high performance Alibaba T-Head XuanTie processor coming to market, we believe it will benefit the RISC-V industry to port RISCV to the Android OS. Over... Read more.
Truechip Introduces Silicon IP for Network on Chip (NOC) Focused for TileLink RISC-V Chips | Truechip
Truechip, the Verification IP Specialist, today announced that it has introduced a Silicon IP to its product offering in addition to its existing Verification IP... Read more.
Build an open source-hardware Allwinner D1s RISC-V Linux SBC for under $10 | Jean-Luc Aufranc, CNX Software
We covered Allwinner D1s RISC-V processor with 64MB built-in RAM a few days ago, and we’ve just found out about Xassette-Asterisk, an open-source hardware board... Read more.