Compsci eggheads bring OpenCL framework to RISC-V to push parallel performance | Gareth Halfacree, The Register
A quartet of computer science boffins have showcased work on bringing the OpenCL programming framework to a wide range of RISC-V chips – improving their suitability... Read more.
What is RISC-V? | Abhishek Jadhav
When it comes to designing your own CPU core, you primarily need to get an open-source ISA (instruction set architecture). This open-source ISA will help the CPU... Read more.
Video: Decade of RISC-V Desktop?! HiFive Unmatched First Look
The world's most powerful RISC-V development platform is here, and we are building a computer with it!
This is a first look at SiFive's new reduced instruction... Read more.
NSITEXE achieves world’s first RISC-V processor with vector extension certified for ISO 26262 ASIL D ready product |
The DR1000C, a data flow processor (DFP) developed by NSITEXE, Inc. (headquartered in Minato Ward, Tokyo, Japan; President and CEO: Yukihide Niimi; hereinafter “NSITEXE”)... Read more.
Chinese Wearable Technology Firm Huami to Launch New OS with Better Understanding of Users | Pandaily
Chinese smart wearable device manufacturer Zepp Health, previously known in the international market as Huami, has announced that it planned to unveil its own OS,... Read more.
Andes certifies Imperas RISC-V Reference Models for the new RISC-V P (SIMD/DSP) extension
Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today announced that Andes Technology Corp., a leading supplier... Read more.
NodeMCU Launches Sub-$5 Espressif ESP32-C3 RISC-V Development Boards | Gareth Halfacree, Hackster.io
The first commercial development boards featuring Espressif's RISC-V-based ESP32-C3, a drop-in replacement for the popular ESP8266, have appeared on the market —... Read more.
RISC-V Bytes: Introduction to Instruction Formats | Daniel Mangum
This is part of a series on the blog where we explore RISC-V by breaking down real programs and explaining how they work. You can view all posts in this series... Read more.
Bringing OpenCL to Commodity RISC-V CPUs | Tine Blaise, Seyong Lee, Jeff Vetter, and Hyesoon Kim, Georgia Institute of Technology
The importance of open-source hardware has been increasing in recent years with the introduction of the RISC-V Open ISA. This has also accelerated the push for support... Read more.
A Look At The ET-SoC-1, Esperanto’s Massively Multi-Core RISC-V Approach To AI | David Schor, WikiChip Fuse
Ask ten different engineers how they would design an AI accelerator and you’ll get ten different ways to arrange the billions of transistors on a modern leading-edge... Read more.