Deep neural networks… IN SPAAACE: Vector-enhanced RISC-V chips could give satellites onboard AI | Gareth Halfacree, The Register
Boffins from the Delft University of Technology (TU Delft) and European Space Agency (ESA) have penned a paper detailing the design of a processor they hope could... Read more.
SiFive Performance P550 Core Sets New Standard as Highest Performance RISC-V Processor IP
New SiFive Performance Family of application processors offers best in class performance, area, and efficiency for a wide variety of markets
SAN MATEO, Calif.,... Read more.
Advanced co-simulation with Renode and Verilator: PolarFire SoC and FastVDMA | Antmicro
Co-simulating HDL has been possible in Renode since the 1.7.1 release, but the functionality - critical for hardware/software co-development as well as FPGA use... Read more.
RISC-V Bytes: Passing on the stack | Daniel Mangum
Read Daniel Mangum's blog series exploring RISC-V by breaking down real programs and explaining how they work.
You can read the blog here.
You can view all posts... Read more.
Imperas Expands Partnership with Valtrix to Address Growing RISC-V Verification Market
Imperas Software Ltd., the leader in RISC-V processor verification technology, today announced a multi-year distribution and support agreement with Valtrix Systems,... Read more.
Video: SSRC Collaborates with Global Universities on RISC-V-Based Secure Flight Computer System | ATRC
TII’s Secure Systems Research Centre (SSRC) has partnered with global universities to develop a RISC-V-Based Secure Flight Computer System. SSRC is a strategic... Read more.
SiFive Deepens RISC-V Core Lineup | William G. Wong, Electronic Design
SiFive keeps cranking out new versions of its RISC-V cores. Its two most recent additions include the Performance P550 core and the Performance P270 vector core,... Read more.
BSC, Codeplay and SiFive help accelerate applications on RISC-V thanks to V-extension support in LLVM
The Barcelona Supercomputing Center (BSC) has been collaborating with Codeplay Software and SiFive to implement support for the RISC-V V-extension v0.10 in the... Read more.
RiVer Core: A RISC-V Core Verification Framework
InCore and Tessolve announce the availability of our open source RISC-V Core Verification tool - RiVer Core. RiVer Core is a python based extensible and scalable... Read more.
On-Board Decision Making in Space with Deep Neural Networks and RISC-V Vector Processors
Stefano Di Mascio, Alessandra Menicucci, Eberhard Gill, Gianluca Furano and Claudio Monteleone
Abstract
The use of deep neural networks (DNNs) in terrestrial... Read more.