EPI Chair Jean-Marc Denis Shares Vision for Future Supercomputers | Tiffany Trader
In this video interview with HPCwire’s Managing Editor Tiffany Trader, Jean-Marc Denis, European Processor Initiative (EPI) chair of the board and head of strategy... Read more.
Intel to Adopt SiFive’s New High-Performance P550 RISC-V Cores With 7nm Platform | Paul Alcorn, Tom’s Hardware
SiFive, the leading designer of chips based on the open source RISC-V architecture, announced its new SiFive Performance line of chips today that support 64-bit... Read more.
NEORV32: a customizable RISC-V SoC #RISCV #FPGA
The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor... Read more.
SiFive Boasts of the “Highest-Performance RISC-V Processor” in Its New P550 Design | Gareth Halfacree, hackster.io
Company claims its latest part is the highest-performing RISC-V core around — but won't be releasing the design under an open license.
RISC-V pioneer SiFive has... Read more.
Canonical enables Ubuntu on SiFive’s HiFive RISC-V boards
With Canonical announcing Ubuntu support for so much new hardware, the announcement of Ubuntu ported to a new architecture can go unnoticed. But today, we have a... Read more.
Extended development tools performance capabilities for Andes RISC-V cores
Extended development tools performance capabilities for Andes RISC-V cores
Latest version of IAR Embedded Workbench for RISC-V adds support for latest Andes RISC-V... Read more.
Intel to Adopt SiFive’s New High-Performance P550 RISC-V Cores With 7nm Platform | Paul Alcorn, Tom’s Hardware
SiFive, the leading designer of chips based on the open source RISC-V architecture, announced its new SiFive Performance line of chips today that support 64-bit... Read more.
Codasip Announces A71X RISC-V Application Core with Dual-Issue Capability
Munich, Germany – June 22, 2021 – Codasip, the leading supplier of customizable RISC-V® processor IP, today announces a new major version of its most advanced... Read more.
Segger and Codasip Announce Cooperation on RISC-V
Monheim am Rhein & Munich, Germany – June 22nd, 2021 – SEGGER and Codasip announce that SEGGER’s J-Link debug probes and its Embedded Studio IDE fully... Read more.
SiFive aims to challenge Arm with new tech, pairs with Intel on effort | Stephen Nellis, Reuters
June 22 (Reuters) - SiFive Inc on Tuesday released a new computing chip design that aims to challenge Arm Ltd's dominance in smartphone chips and said it would pair... Read more.