European supercomputer test chip tapes out | eeNews, Peter Clarke
The EPAC 1.0 test chip is now ready to be sent to fabrication, It contains a number of accelerator cores some based on RISC-V instruction set architecture.
The EPI,... Read more.
VIDEO: TII’s Secure Systems Research Centre Joins RISC-V International | ATRC
#TII’s Secure Systems Research Centre (#SSRC) has become a strategic member of RISC-V International, an organisation which directs the future development and drives... Read more.
Technology Innovation Institute’s Centre Joins RISC-V International | Faizan Hashmi
ABU DHABI, (UrduPoint / Pakistan Point News / WAM - 02nd Jun, 2021) Technology Innovation Institute (TII), the applied research pillar of Abu Dhabi’s Advanced... Read more.
HiFive ISS | UKRocketry
Connecting to the ISS crew manifest using an online API, the BBC HiFive and its onboard ESP32 using Micropython.... Read more.
Continuing Challenges For Open-Source Verification | BRIAN BAILEY, Semiconductor Engineering
Experts at the Table: This is the last part of the series of articles derived from the DVCon panel that discussed Verification in the Era of Open Source. It takes... Read more.
EPI EPAC1.0 RISC-V Test Chip Taped-out | Design & Reuse
June 1, 2021 -- The European Processor Initiative (EPI) https://www.european-processor-initiative.eu/, a project with 28 partners from 10 European countries, with... Read more.
European Processor Initiative Announces EPAC1.0 RISC-V Test Chip Taped-out | HPCWire
June 1, 2021 — The European Processor Initiative (EPI), a project with 28 partners from 10 European countries, with the goal of helping the EU achieve independence... Read more.
VIDEO: RISC-V MYTH Workshop Promo video – 2 | VLSI System Design
*RISC-V 32-bit Instruction Type Decode logic design in 120sec* Just imagine what all things you can do in RISC-V MYTH 5-day workshop. Many participants have changed... Read more.
VIDEO: Keynote Session: Hypervisor Extensions in RISC-V – Robert Eshleman, Vates SAS | The Xen Project
Keynote Session: Hypervisor Extensions in RISC-V - Robert Eshleman, Vates SAS This talk presents the virtualization capabilities offered by the RISC-V Hypervisor... Read more.
SEGGER’s emRun Runtime Library Licensed by SiFive for Superior Code Size and Performance Improvements | Design & Reuse
Monheim am Rhein, Germany – May 31, 2021 -- The SEGGER emRun runtime library is available as part of the recently announced SiFive 21G1 release. SiFive’s focus... Read more.