Imperas Collaborates with Mentor on RISC-V Core RTL Coverage Driven Design Verification Analysis
http://www.imperas.com/articles/imperas-collaborates-with-mentor-on-risc-v-core-rtl-coverage-driven-design-verification]]>... Read more.
SILICON | China’s Progress on Homegrown CPUs | Stewart Randall, TechNode
problems with EDA tools and chip fabrication. It isn’t all doom and gloom for China, though, and I’d like to talk about some areas where China is doing better.... Read more.
FPGA System-on-Module for Power-Efficient Computation | Anis Zenadji, IEN Europe
The specialist in embedded services and products ARIES will present its brand-new System-on-Module (SoM) M100PFS at Embedded World 2020 (February 25 to 27, 2020... Read more.
RVSoC Offers a Lightweight Linux-Capable RISC-V Core in Just 5,000 Lines of Verilog | Gareth Halfacree, Hackster.io
A team from the School of Computing at the Tokyo Institute of Technology have developed a portable and Linux-capable RISC-V system-on-chip (SoC) design in just 5,000... Read more.
Fast Access to Accelerators: Enabling Optimized Data Transfer with RISC-V | Shubu Mukherjee, Chief SoC Architect of SiFive
https://www.sifive.com/blog/fast-access-to-accelerators-enabling-optimized-data-transfer-with-risc-v]]>... Read more.