SiFive Shield is an Open Security Platform for RISC-V Processors | Jean-Luc Aufranc, CNX Software
https://www.cnx-software.com/2019/10/24/sifive-shield-open-security-platform-for-risc-v-processors/ https://www.cnx-software.com/2019/10/24/sifive-shield-open-security-platform-for-risc-v-processors/]]>... Read more.
OneSpin Shows How to Achieve IC Integrity at DVCon Europe | OneSpin
OneSpin’s verification experts present RISC-V integrity tutorial and functional safety session MUNICH, GERMANY –– October 24, 2019 –– OneSpin® Solutions,... Read more.
RISC-V Challenges and Opportunities | Ed Sperling, Semiconductor Engineering
Rambus’ Security Division; Jerry Ardizzone, vice president of worldwide sales at Codasip; Megan Wachs, vice president of engineering at SiFive; and Rishiyur... Read more.
SiFive Shield: An Open, Scalable Platform Architecture for Security | James Prior, SiFive
https://www.sifive.com/blog/sifive-shield-an-open-scalable-platform-architecture]]>... Read more.
GCC Support for the Draft Bit Manipulation Extension for RISC-V | Maxim Blinov, Embescom
https://www.embecosm.com/2019/10/22/gcc-risc-v-bit-manipulation-extension/]]>... Read more.
LLVM Support for the Draft Bit Manipulation Extension for RISC-V | Paolo Savini, Embecosm
RISC-V Instruction Set Manual describes the current status of the RISC-V ISA and its extensions. Among these there’s a mention of the ‘B’ extension that is... Read more.
Why RISC-V Will Prevail | Marc Sauter, Golem
https://www.golem.de/news/offene-prozessor-isa-wieso-risc-v-sich-durchsetzen-wird-1910-141978.html]]>... Read more.