Startup plans customizable RISC-V edge AI speech processor | Nick Flaherty, EE News Europe
AONDevices has developed an efficient edge AI denoising technology for applications that require minimal power and latency running on its forthcoming accelerator... Read more.
Imagination, GHS team for RTOS and tools on RISC-V CPUs | Nick Flaherty, EENews Europe
Green Hills Software has ported its µ-velOSity safety- and security-certified real-time operating system (RTOS) to the real time RISC-V cores developed by Imagination... Read more.
Agile Analog launches first complete RISC-V analog IP subsystem at RISC-V Summit Europe
Agile Analog, the customisable analog IP company, is launching the first complete analog IP subsystem for RISC-V applications at the RISC-V Summit Europe in Barcelona... Read more.
Interview with Calista Redmond – RISC-V summit Barcelona
At the RISC-V summit in Barcelona eeNews is meeting up with Calista Redmond. She is the CEO of RISC-V International. In our conversation we are talking about what... Read more.
Configurable 64-bit RISC-V IP Targets Machine Learning, Other Advanced Apps | Alix Paultre, Electronic Design
Configurable high-bandwidth RISC-V cores with vector units can be made to directly address challenging applications like machine learning, AI, and other cutting-edge... Read more.
Computing at the Ultimate Edge – Space | Wisse Hettinga, EENews Europe
eeNews Europe is meeting up with Gerard Rauwerda, Business Developer with Technolution. We discuss the RISC-V developments over the years and the role Technolution... Read more.
Safety Critical Real-Time Operating System, SAFERTOS® Available With MiV_RV32 Soft CPU
SAFERTOS® is a real-time operating system (RTOS) designed specifically for use in safety-critical systems. WITTENSTEIN high integrity systems is a Mi-V Ecosystem... Read more.
The RISC-V Report – interviewing the key players (2017-2023)
Take time for the The RISC-V Summit in Barcelona and connect the dots of this Open Instruction Set Architecture In 2017 we had the opportunity to interview Krste... Read more.
Agile Analog launches first complete RISC-V analog IP subsystem
Agile Analog has brought together its customisable IP blocks to create the first complete analog IP subsystem for battery-powered RISC-V chips. The initial subsystem... Read more.
Complete RISC-V analog IP subsystem targets IoT | Jean-Pierre Joosting, EE News Europe
Agile Analog is offering the first complete analog IP subsystem for RISC-V applications at the RISC-V Summit Europe in Barcelona. The initial subsystem includes... Read more.