Integrated IP Core Generation Workflow for Microchip SoC FPGAs With MathWorks®
By: Puneet Kumar Learn more about IP Core Generation workflow from MATLAB® R2022A release onwards for PolarFire® SoC FPGA and SmartFusion® 2 family of Microchip... Read more.
RISC-V compiler toolset targets automotive functional safety
TASKING has introduced the industry’s first ISO 26262 and ISO/SAE 21434 compliant compiler toolset, designated VX-Toolset for RISC-V. The compiler facilitates... Read more.
Imagination Reveals RISC-V Processor at Embedded World 2024
Following up on our previous reporting on the changes at UK-based Imagination Technologies, the company announced a new RISC-V applications processor IP, the Imagination... Read more.
SiFive Unveils the HiFive Premier P550, the First Commercially Available Out-of-order RISC-V Development Board
HiFive Premier P550 is the highest performance RISC-V development board on the market, offering developers unmatched flexibility and performance Nuremberg, Germany... Read more.
Meeting RISC-V Demands: S2C’s Tailored Offerings
RISC-V, an open standard instruction set architecture (ISA), has captured the imaginations of engineers and innovators worldwide due to its simplicity and accessibility.... Read more.
Imagination’s new Catapult CPU is driving RISC-V device adoption
Imagination Technologies today unveils the next product in the Catapult CPU IP range, the Imagination APXM-6200 CPU: a RISC-V application processor with compelling... Read more.
IAR, Nuclei, and MachineWare Join Forces To Speed Up Innovation in RISC-V ASIL Compliant Automotive Solution
Uppsala, Sweden, April 8, 2024 – IAR, the leader in software solutions and services for embedded development, has joined forces with Nuclei System Technology... Read more.
Imagination’s New Catapult CPU Is Driving RISC-V Device Adoption
LONDON–(BUSINESS WIRE)–Imagination Technologies today unveils the next product in the Catapult CPU IP range, the Imagination APXM-6200 CPU: a RISC-V... Read more.
RISC-V Cryptography Evolution: High Assurance and Post-Quantum Cryptography (RWC 2024)
NAME is a talk presented by Markku-Juhani O. Saarinen at RWC 2024. This was the first talk in a session on post-quantum implementations, chaired by Thomas Prest.... Read more.
[VIDEO] RISC-V 2024 Update: RISE, AI Accelerators & More
RISC-V annual update, covering developments in RISC-V hardware and software including RISE, Quintaris, and AI accelerators. Watch the full video.... Read more.