Developing standards-based verification environments for extensible RISC-V processor cores | Kevin McDermott, Imperas Software
One of the appealing things about open-source is that it invites modification to the underlying technology. In the case of the RISC-V instruction set architecture... Read more.
OpenHW Group highlights how verification is a key aspect of the open-source CORE-V processor IP
The RISC-V ISA (Instruction Set Architecture) permits a range of possibilities for processor implementation with a modular approach for standard and custom extensions.... Read more.
OpenHW open source CORE-V processor IP: a RISC-V story that leads with verification
Fig. 1. OpenHW: CORE-V processor features for CVE4 & CVA6 [vc_column column_padding="no-extra-padding" column_padding_tablet="inherit" column_padding_phone="inherit"... Read more.
Getting Started with RISC-V Verification
By Kevin McDermott, Vice President of Marketing at Imperas Software Ltd. Design Verification (DV) test planning using a trusted SoC methodology for RISC-V processor... Read more.