In the Media

SEGGER today announces its partnership with HPMicro Semiconductor Inc. (HPMicro), a leading supplier of high-performance MCUs and embedded solutions. The partnership focuses on making SEGGER’s top-rated, multi-platform IDE Embedded Studio…

Codasip has launched two 32bit RISC-V processor cores that can be optimised for machine learning applications. The L31 and L11 are the latest cores optimized for customization to run machine…

Renesas offers the RZ/Five general-purpose MPU, its first built around a 64-bit RISC-V core from Andes Technology. The RZ/Five is optimized to provide the performance and peripheral functions required for…

MangoPi-Nezha MQ tiny developer board with Allwinner F133-A (aka Allwinner D1s) RISC-V processor with 64MB on-chip RAM has just launched on Crowd Supply for $39, and delivery is expected in July 2022. The…

At this year’s (virtual) functional design and verification conference, DVCon US 2022, the RISC-V Verification Interface (RVVI) was announced by Imperas Software. The interface is available at github. The draft open standard defines…

The latest ImperasDV test suite for PMP covers the full envelope of configuration options. Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the beta release of the ImperasDV…

M5Stamp C3U is an update of the M5Stamp C3 RISC-V IoT module with heat-resistant cover, support for WiFi 4 and Bluetooth 5.0, that does without CH9102 USB to TTL chip, relying instead…

The open standard ISA (Instruction Set Architecture) of RISC-V offers developers a wide range of standard extensions and options that support the design of an optimised processor. The RISC-V Privileged…

The latest ImperasDV test suite for PMP covers the full envelope of configuration options. Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the beta release of the…