SiFive, the leading designer of chips based on the open source RISC-V architecture, announced its new SiFive Performance line of chips today that support 64-bit operating systems, like Linux. The…
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The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs…
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Company claims its latest part is the highest-performing RISC-V core around — but won't be releasing the design under an open license. RISC-V pioneer SiFive has once again laid claim…
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With Canonical announcing Ubuntu support for so much new hardware, the announcement of Ubuntu ported to a new architecture can go unnoticed. But today, we have a big one. Working …
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Extended development tools performance capabilities for Andes RISC-V cores Latest version of IAR Embedded Workbench for RISC-V adds support for latest Andes RISC-V processor technology, including AndeStar™ V5 RISC-V Performance…
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Latest version of IAR Embedded Workbench for RISC-V adds support for latest Andes RISC-V processor technology, including AndeStar™ V5 RISC-V Performance Extension Uppsala, Sweden—June 23, 2021—IAR Systems®, the future-proof supplier…
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SiFive, the leading designer of chips based on the open source RISC-V architecture, announced its new SiFive Performance line of chips today that support 64-bit operating systems, like Linux. The…
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Munich, Germany – June 22, 2021 – Codasip, the leading supplier of customizable RISC-V® processor IP, today announces a new major version of its most advanced processor IP core: the…
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Monheim am Rhein & Munich, Germany – June 22nd, 2021 – SEGGER and Codasip announce that SEGGER’s J-Link debug probes and its Embedded Studio IDE fully support Codasip’s RISC-V processors,…
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June 22 (Reuters) - SiFive Inc on Tuesday released a new computing chip design that aims to challenge Arm Ltd's dominance in smartphone chips and said it would pair with…
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