Imagination Technologies (“Imagination”) today announced a new investment by funds managed by affiliates of Fortress Investment Group LLC (“Fortress”). Under the terms of the agreement, Fortress has provided Imagination with a…
CHANDLER, Ariz., JULY 9, 2024 — The world has changed dramatically in the two decades since the debut of what was then considered a trail-blazing space-grade processor used in NASA missions…
July-8 th, 2024, Kochi, India. Embedded tools developer Ashling is pleased to partner with C-DAC, supporting their VEGA RISC-V based multi-core microprocessor family with our RiscFree™ C/C++ SDK and Opella-XD…
In today’s landscape of generative AI, IoT, and more, the demand for advanced RISC-V core IP is rapidly escalating. As technology becomes increasingly software-driven, the industry has shifted from developing…
In the world of processor development, flexibility is becoming a distinct advantage. As an open-standard instruction set architecture (ISA), the fifth iteration of reduced instruction set computing (RISC-V) embodies this…
Silicon Valley, CA and Eindhoven, NL – June 27, 2024 – Axelera AI, the leading provider of purpose-built AI hardware acceleration technology for generative AI and computer vision inference, today announced…
Munich, Germany — The European tech landscape is witnessing a notable evolution with the growing embrace of RISC-V, the open-source instruction set architecture. During the recent RISC-V Summit Europe, leading…
AI start-up Tenstorrent has announced the commercial release of its Wormhole processors, built to power AI accelerators to compete with Nvidia. Wormhole will power the new Wormhole n150 and n300…
RISC-V ISA is almost 15-year old and RISC-V hardware has been popping up regularly for a while. Until recently it was difficult to find a board with RISC-V Vector support, in particular…
Eggtronic in Italy has added reprogrammable flash memory to its EPIC RISC-V mixed-signal power controller. The Eggtronic RISC-V EPIC 2.0 Flash series provides more flexibility through the design process, while…