SAN JOSE, Calif., June 20, 2024 (GLOBE NEWSWIRE) -- Breker Verification Systems, whose product portfolio solves challenges across the functional and system verification process for large, complex semiconductors, today unwrapped its…
As RISC-V gains traction as an open-source alternative to Arm, several companies have announced partnerships and research to bolster the ISA. Forecasts show that AI will continue to fuel RISC-V…
Welcome to the Ultimate Guide to RISC-V Architecture. In this course, our Founder and CEO, Mr. P R Sivakumar, explains the layered architecture of RISC-V open ISA and how we…
Synopsys has expanded its ARC processor portfolio to include a family of RISC-V processors. This was originally reported on SemiWiki last October. There is also a recent in-depth article on the make-up…
Sipeed has announced a new entry in its Lichee RISC-V family, this time putting its high-performance Lichee 4A RISC-V system-on-module into a full-size laptop chassis: the Lichee Book 4A. "Lichee…
The IAR safety-certified C-STAT tool is now available in the Functional Safety editions of IAR Embedded Workbench for RISC-V, ARM, and Renesas RL78 architectures. The latest IAR Embedded Workbench for…
Today, RISC-V pioneer DeepComputing announced that their first RISC-V Mainboard, compatible with the Framework Laptop 13, is about to be released. Sporting a RISC-V StarFive JH7110 SoC, this groundbreaking Mainboard was…
Alexander Conklin, Head of Hardware Engineering, Rain AI The compute intensive demands of AI workloads have given rise to a new era in accelerator design. In this talk we’ll take…
RISC-V Banana Pi BPI-F3 development board review and specifications, including demonstrations running Bianbu OS from SpaceMIT (who also developed the K1 RISC-V SoC on which this SBC is based). Watch…
DeepComputing partners with Canonical to unveil a huge boost to the DC-ROMA RISC-V Laptop family The DC-ROMA RISC-V Laptop II is the world’s first RISC-V laptop pre-installed and powered by…