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Andes Webinar 2023 | Andes President and CTO, Dr. Charlie Su, Andes Technology
RISC-V Reaches a Turning Point | James Sanders and Wayne Lam, CCS Insights
Removing the Risk from RISC-V using the RISC-V Trace Standard | Peter Shields, Siemens
El Correo Libre Issue 58 | Gareth Halfacree, FOSSSi Foundation
Espressif ESP32-P4 – A 400 MHz general-purpose dual-core RISC-V microcontroller | Jean-Luc Aufranc, CNX Software
Everyone deserves a Pinecil | Chris Person, The Verge
My open source silicon highlights of 2022 and goals for 2023 | Matt Venn, Zero To ASIC CourseMy open source silicon highlights of 2022 and goals for 2023 | Matt Venn, Zero To ASIC Course
Implementation of RISCduino core using a Hierarchical Design Flow | Dinesh Annayya, OpenRoad
MIPS Rolls Out Its First RISC-V Processor Core – It’s a Big ‘Un | Steve Leibson, EE Journal
A chip design that changes everything: 10 Breakthrough Technologies 2023 | Sophia Chen, MIT Technology Review
RISC-V Hibernation Support / Suspend-To-Disk Nears The Linux Kernel | Michael Larabel, Phoronix
RISC-V Guns for Raspberry Pi, Legacy Chips | Lucas Laursen, IEEE Spectrum
RISC-V Serves Up Open-Source Possibilities for the Future | Cabe Atwell, Electronic Design
Joint venture unveils world’s first RISC-V laptop | Robin Mitchell, Electropages
Imperas announces the latest updates to RVVI and welcomes the adoption by many leading RISC V processor developers | Imperas Software
Open Standard RISC-V Verification Interface (RVVI) for SOC testing | Nick Flaherty, EE News Europe
China pins hopes on local RISC-V start-ups to crack Western monopoly on CPU chips | Che Pan, South China Morning Post
ISA Extension For Low-Precision NN Training On RISC-V Cores | Luca Bertaccini, Gianna Paulin, Tim Fischer, Stefan Mach, Luca Benini, Semiconductor EngineeringEurope steps up as RISC-V ships 10bn cores | Nick Flaherty, EE News Europe
RISC-V Opens the Door on 48-bit Computing | Agam Shah, HPC Wire
Imperas and Breker partner for Risc-V system-level verification | Steve Bush, Electronics Weekly
First RISC-V-Based SoC FPGA Enters Mass Production | Microchip Technology, EE Time Asia
SiFive arrives in Cambridge to hire 100 for ascendant RISC-V computing | Mike Scialom, Cambridge Independent
Andes Webinar 2023 | Andes President and CTO, Dr. Charlie Su, Andes TechnologyAndes Webinar is the annual opportunity to get the information about RISC-V technology trends, innovative Andes solutions and more. Andes President and CTO, Dr. Charlie…
RISC-V Reaches a Turning Point | James Sanders and Wayne Lam, CCS InsightsRISC-V, introduced in 2010, is the first novel instruction set architecture (ISA) to gain market traction in decades. New design firms such as SiFive —…
Removing the Risk from RISC-V using the RISC-V Trace Standard | Peter Shields, SiemensWith the growing maturity of the RISC-V ISA, chip companies now have a wealth of options for implementing RISC-V cores in their latest product. At…
El Correo Libre Issue 58 | Gareth Halfacree, FOSSSi FoundationPreparations Begin for Latch-Up 2023 The FOSSi Foundation is very pleased to announce that Latch-Up will go ahead in 2023! This marks a triumphant return…
Espressif ESP32-P4 – A 400 MHz general-purpose dual-core RISC-V microcontroller | Jean-Luc Aufranc, CNX SoftwareEspressif ESP32-P4 is a general-purpose dual-core RISC-V microcontroller clocked at up to 400 MHz with AI instructions extension, numerous I/Os, and security features. It also…
Everyone deserves a Pinecil | Chris Person, The VergeLearning to solder was a life-changing experience for me, but it can seem daunting. You aren’t just screwing and unscrewing parts — you are melting…
My open source silicon highlights of 2022 and goals for 2023 | Matt Venn, Zero To ASIC CourseMy favourite moments of 2022 and goals and thoughts for 2023! Watch the full video.
My open source silicon highlights of 2022 and goals for 2023 | Matt Venn, Zero To ASIC CourseMy favourite moments of 2022 and goals and thoughts for 2023! Watch the full video.
Implementation of RISCduino core using a Hierarchical Design Flow | Dinesh Annayya, OpenRoadDinesh Annaya is an ardent Open-Source EDA enthusiast and an expert user of OpenROAD and OpenLane. He developed a baseline RISCduino SoC, a single, 32…
MIPS Rolls Out Its First RISC-V Processor Core – It’s a Big ‘Un | Steve Leibson, EE JournalEven though the company had telegraphed its big move, MIPS’s adoption of the RISC-V ISA for its future processor cores hit me like a ton…
A chip design that changes everything: 10 Breakthrough Technologies 2023 | Sophia Chen, MIT Technology ReviewComputer chip designs are expensive and hard to license. That’s all about to change thanks to the popular open standard known as RISC-V. Ever wonder…
RISC-V Hibernation Support / Suspend-To-Disk Nears The Linux Kernel | Michael Larabel, PhoronixWhile the open RISC-V processor architecture has proven to be highly successful, one of the features that it hasn't yet supported with the Linux kernel…
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RISC-V Guns for Raspberry Pi, Legacy Chips | Lucas Laursen, IEEE SpectrumTwo hardware makers are planning to offer chips later this year featuring the RISC-V free and open architecture standard, joining the US $180 Linux-capable StarFive…
RISC-V Serves Up Open-Source Possibilities for the Future | Cabe Atwell, Electronic DesignThis article is part of the TechXchange: RISC-V: The Instruction-Set Alternative What you’ll learn: What is RISC-V? The basics of RISC-V. Applications and uses of…
Joint venture unveils world’s first RISC-V laptop | Robin Mitchell, ElectropagesAs RISC-V continues to push the boundaries of open-source computing, a joint venture between DeepComputing and Xcalibyte has developed the world’s first RISC-V laptop set…
Imperas announces the latest updates to RVVI and welcomes the adoption by many leading RISC V processor developers | Imperas SoftwareImperas Software Ltd., the leader in RISC-V simulation solutions, today announced the latest updates for RVVI (RISC-V Verification Interface) for RISC-V processor verification with virtual peripherals to support asynchronous…
Open Standard RISC-V Verification Interface (RVVI) for SOC testing | Nick Flaherty, EE News EuropeImperas Software in the UK has extended the RVVI (RISC-V Verification Interface) with virtual peripherals to support asynchronous events and system level interrupts. RVVI is an…
China pins hopes on local RISC-V start-ups to crack Western monopoly on CPU chips | Che Pan, South China Morning PostChina is seeing a chance to improve its self sufficiency in microprocessors, the heart of every smart device, through the open-standard RISC-V chip design architecture,…
ISA Extension For Low-Precision NN Training On RISC-V Cores | Luca Bertaccini, Gianna Paulin, Tim Fischer, Stefan Mach, Luca Benini, Semiconductor EngineeringAbstract “Low-precision formats have recently driven major breakthroughs in neural network (NN) training and inference by reducing the memory footprint of the NN models and…
Europe steps up as RISC-V ships 10bn cores | Nick Flaherty, EE News EuropeIt may come as a surprise that over 10 billion RISC-V processor cores have shipped. After all, it took ARM 17 years to reach that…
RISC-V Opens the Door on 48-bit Computing | Agam Shah, HPC WireThere’s a growing interest among silicon providers backing RISC-V to introduce 48-bit computing in custom chips to meet their specific requirements. The 48-bit long instructions…
Imperas and Breker partner for Risc-V system-level verification | Steve Bush, Electronics WeeklyRISC-V simulation company Imperas Software has announced a partnership with Breker Verification Systems, a provider of test content synthesis for verification environments, to develop interfaces…
First RISC-V-Based SoC FPGA Enters Mass Production | Microchip Technology, EE Time AsiaThe first SoC field programmable gate array (FPGA) to support the royalty-free RISC-V open Instruction Set Architecture (ISA) has entered volume production, marking a major…
SiFive arrives in Cambridge to hire 100 for ascendant RISC-V computing | Mike Scialom, Cambridge IndependentSiFive, the California-based founder and leader of RISC-V computing, has opened its new UK Research & Development (R&D) Centre at WeWork on Station Road –…