No recent posts listed
RISC-V Hibernation Support / Suspend-To-Disk Nears The Linux Kernel | Michael Larabel, Phoronix
Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core | Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Marco Ottavi and Mauro OlivieriTCADer: A Tightly Coupled Accelerator Design framework for heterogeneous system with hardware/software co-design based on RISC-V | Wenqing Li, Tianyi Liu, Ziyuan Xiao HanQi, Weipu Zhu, Jian Wang
VisionFive 2: RISC-V Quad Core Low Cost SBC | Christopher Barnatt, Explaining Computers
Podcast EP135: Democratizing HPC & AI | Inspire Semiconductor, Semiwiki.com
Alexander Williams’ FiveForths Is a “Hand-Written” RISC-V Assembly Forth for Microcontrollers | Gareth Halfacree, Hackster.io
Week In Review: Design, Low Power | Marie C. Baca, Semiconductor EngineeringRecommendation for a holistic secure embedded ISA extension | Florian Stolz, Marc Fyrbiak, Pascal Sasdrich, Tim Güneysu
MangoPi MQ-PRO Review: RISC-V Raspberry Pi Zero Alternative? | Learn Embedded Systems
Google to Make RISC-V a Major Platform for Android | Robin Mitchell, ElectropagesHow Secure Are RISC-V Chips? | Jeff Goldman, Semiconductor Engineering
Grokking RISC-V Vector Processing | Erik Engheim, ITNext
SiFive arrives in Cambridge to hire 100 for ascendant RISC-V computing | Mike Scialom, Cambridge Independent
Imperas Announces Partnership with Breker to Drive Rigorous Processor-to-System Level Verification for RISC-V | Imperas Software
seL4 userspace debugging with GDB extensions in Renode | AntmicroImperas announce the latest RISC-V test suites are now available free with riscvOVPsimPlus | Imperas Software
Upcoming RISC-V laptop promises free silicon upgrades | Scharon Harding, Ars Technica
First RISC-V laptop arrives | Nick Farrell, FudzillaTU Dresden: Tile-based Multi-Core Architecture for Heterogeneous RISC-V Processors Suitable for FPGA Platforms | Semiconductor Engineering
Take note, Arm: The world’s first RISC-V laptop is now available for preorder | Joel Khalili, Tech Radar
First native RISC-V laptop readies for market | Nick Flaherty, EE News Europe
The first laptop with a RISC-V processor is coming | Brad Linder, Liliputing
One of the first RISC-V laptops may ship in September, has an NFT hook | Dylan Martin, The RegisterEspressif Unveils Its First Dual-Band Wi-Fi 6 and BLE RISC-V Part for the IoT: The ESP32-C5 | Gareth Halfacree, Hackster.io
RISC-V Hibernation Support / Suspend-To-Disk Nears The Linux Kernel | Michael Larabel, PhoronixWhile the open RISC-V processor architecture has proven to be highly successful, one of the features that it hasn't yet supported with the Linux kernel…
Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core | Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Marco Ottavi and Mauro OlivieriAbstract: Functional safety is a key requirement in several application domains in which microprocessors are an essential part. A number of redundancy techniques have been…
TCADer: A Tightly Coupled Accelerator Design framework for heterogeneous system with hardware/software co-design based on RISC-V | Wenqing Li, Tianyi Liu, Ziyuan Xiao HanQi, Weipu Zhu, Jian WangAbstract - Domain-specific architectures (DSAs) or hardware accelerators are typical innovations that are leading computer architecture into a new golden age. In a heterogeneous system,…
VisionFive 2: RISC-V Quad Core Low Cost SBC | Christopher Barnatt, Explaining ComputersStarFive VisionFive 2 RISC-V SBC review, including a demo of an engineering release of Debian, and of Python GPIO control. My previous “Explaining RISC-V” video…
Podcast EP135: Democratizing HPC & AI | Inspire Semiconductor, Semiwiki.comDan is joined by Doug Norton, VP of Business Development for Inspire Semiconductor, an Austin-based high performance computing chip design company. He is also the President of…
Alexander Williams’ FiveForths Is a “Hand-Written” RISC-V Assembly Forth for Microcontrollers | Gareth Halfacree, Hackster.ioWritten in RISC-V assembly, this tiny Forth port is open source and fully functional on the Longan Nano microcontroller. Developer Alexander Williams has written and…
Week In Review: Design, Low Power | Marie C. Baca, Semiconductor EngineeringTop Of The News Google announced it will support the RISC-V architecture with the Android open-source operating system. In a keynote at the RISC-V Summit, Lars Bergstrom, Google’s director of engineering for…
Recommendation for a holistic secure embedded ISA extension | Florian Stolz, Marc Fyrbiak, Pascal Sasdrich, Tim GüneysuAbstract Embedded systems are a cornerstone of the ongoing digitization of our society, ranging from expanding markets around IoT and smart-X devices over to sensors…
MangoPi MQ-PRO Review: RISC-V Raspberry Pi Zero Alternative? | Learn Embedded SystemsIn a time when Raspberry Pi’s are few and far between, alternative options such as the MangoPi MQ-PRO are increasingly interesting. In this review we…
Google to Make RISC-V a Major Platform for Android | Robin Mitchell, ElectropagesAs RISC-V continues to increase in popularity, many businesses are now turning to the processor architecture, including Google, which has just recently announced that RISC-V…
How Secure Are RISC-V Chips? | Jeff Goldman, Semiconductor EngineeringOpen source by itself doesn’t guarantee security. It still comes down to the fundamentals of design. When the Meltdown and Spectre vulnerabilities were first uncovered…
Grokking RISC-V Vector Processing | Erik Engheim, ITNextA friendly introduction to the core concepts in the RISC-V “V” Vector Extension, version 1.0. While the basic idea of vector processing is simple, the…
No recent posts listed
No recent posts listed
No recent posts listed
No recent posts listed
SiFive arrives in Cambridge to hire 100 for ascendant RISC-V computing | Mike Scialom, Cambridge IndependentSiFive, the California-based founder and leader of RISC-V computing, has opened its new UK Research & Development (R&D) Centre at WeWork on Station Road –…
Imperas Announces Partnership with Breker to Drive Rigorous Processor-to-System Level Verification for RISC-V | Imperas SoftwareImperas Software Ltd., the leader in RISC-V simulation solutions, today announced a partnership with Breker Verification Systems, a leading provider of advanced test content synthesis solutions for…
seL4 userspace debugging with GDB extensions in Renode | AntmicroDebugging is an integral part of the embedded systems development process especially in the context of userspace applications running inside an OS, where it can…
Imperas announce the latest RISC-V test suites are now available free with riscvOVPsimPlus | Imperas SoftwareImperas Software Ltd., the leader in RISC-V simulation solutions, today announced the latest RISC-V test suites and updates to the free riscvOVPsimPlus reference model, simulator and test suites.…
Upcoming RISC-V laptop promises free silicon upgrades | Scharon Harding, Ars TechnicaThe world's first laptop to use the RISC-V open source instruction set architecture (ISA) will reportedly start shipping in September. The Roma laptop is available for…
First RISC-V laptop arrives | Nick Farrell, FudzillaThe world’s first RISC-V laptop has just hit the shelves to a collective yawn from reviewers. The ROMA development platform boasts the forthcoming quad-core RISC-V…
TU Dresden: Tile-based Multi-Core Architecture for Heterogeneous RISC-V Processors Suitable for FPGA Platforms | Semiconductor EngineeringNew technical paper titled “AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors” from researchers at Technische Universitaet Dresden (TU Dresden). Read the full…
Take note, Arm: The world’s first RISC-V laptop is now available for preorder | Joel Khalili, Tech RadarA new laptop billed as the first ever to run atop RISC-V-based silicon is now available to pre-order (opens in new tab) online. The product…
First native RISC-V laptop readies for market | Nick Flaherty, EE News EuropeARM has spent decades working with partners on ARM-based laptops. Its open standard competitor, RISC-V, is looking to catch up fast with the first developers…
The first laptop with a RISC-V processor is coming | Brad Linder, LiliputingThe first laptop powered by a processor that uses RISC-V architecture is up for pre-order. The “Roma” laptop comes from a collaboration between China’s DeepComputing…
One of the first RISC-V laptops may ship in September, has an NFT hook | Dylan Martin, The RegisterIt seems promoters of RISC-V weren't bluffing when they hinted a laptop using the open-source instruction set architecture would arrive this year. Pre-orders opened Friday…
Espressif Unveils Its First Dual-Band Wi-Fi 6 and BLE RISC-V Part for the IoT: The ESP32-C5 | Gareth Halfacree, Hackster.ioEspressif has announced its first RISC-V chip — and the industry's first, it claims — to offer dual-band Wi-Fi 6 and Bluetooth Low Energy (BLE)…