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Andes teams on FPGA prototyping for RISC-V development
S2C and Andes Technology Collaborating to Accelerate Advanced RISC-V SoC Development
Andes Technology and Imagination Technologies Showcase Android 15 on High-Performance RISC-V Based Platform
RISC-V RVA23—A Major Milestone
RISC-V International Newsletter – April 2025
Cost-Effective and Scalable: A Smarter Choice for RISC-V Development
Testing Infineon’s virtual automotive RISC-V chip
[VIDEO] OpenHW Foundation RISC-V Cores: Empowering the Hardware Revolution for SDV
Canonical Adds the Orange Pi RV2 to Its List of Officially-Supported Ubuntu-Capable RISC-V Boards
Podcast EP282: An Overview of Andes Focus on RISC-V and the Upcoming RISC-V CON
Ubuntu developer images now available for OrangePi RV2: a low-cost RISC-V SBC
Enhancing Commercial Software Adaptation with XuanTie Optimized Computing Libraries (Vectorization)
World’s First RISC-V Pad with LTE Launched by DeepComputing at RISC-V Summit 2023
Enabling Secure Open Source ML Products with Open Se Cura
Integrating PikeOS with Microchip’s RISC-V based PolarFire® SoC FPGA | PikeOS: A Versatile Hypervisor-RTOS
[Case Study] SuperTest – helping TrustInSoft guarantee its customers 100% bug-free source code
Quick Time-To-Market with a Compact and Powerful Microchip PolarFire® SoC FPGA System on Module
Accelerating the Open Source Software Ecosystem with RISC-V Labs
Debugging RISC-V processors using E-Trace
S2C’s FPGA Prototyping Accelerates Iterations of XiangShan RISC-V Processor
RISC-V is Here! RISC-V Summit North America Showcases Innovation, Products, Boards, Community
Journeying Beyond AI: Unleashing the Art of VerificationDPI support in Renode for HDL co-simulation with Verilator and Questa
RISC-V: An Open Standard – Backed by a Global Community – to Enable Open Computing for All
World’s First RISC-V Pad with LTE Launched by DeepComputing at RISC-V Summit 2023Enabling Secure Open Source ML Products with Open Se CuraIntegrating PikeOS with Microchip’s RISC-V based PolarFire® SoC FPGA | PikeOS: A Versatile Hypervisor-RTOS[Case Study] SuperTest – helping TrustInSoft guarantee its customers 100% bug-free source codeQuick Time-To-Market with a Compact and Powerful Microchip PolarFire® SoC FPGA System on ModuleAccelerating the Open Source Software Ecosystem with RISC-V LabsDebugging RISC-V processors using E-TraceS2C’s FPGA Prototyping Accelerates Iterations of XiangShan RISC-V ProcessorRISC-V is Here! RISC-V Summit North America Showcases Innovation, Products, Boards, CommunityJourneying Beyond AI: Unleashing the Art of VerificationDPI support in Renode for HDL co-simulation with Verilator and QuestaRISC-V: An Open Standard – Backed by a Global Community – to Enable Open Computing for All
Memory Safety Will Be Key to Tackle Fundamental Cyber Security
Imagination reveals new power-efficient DXTP GPU for laptops and mobile devices
Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
High-schooler creates LinuxPDF: Running Linux on a RISC-V emulator inside a PDF file
The RISC-V Architecture: 16 Boards and MCUs You Should Know
Cortus MINERVA Out-of-Order 4GHz 64-bit RISC-V Processor Platform targets automotive applications
Fedora Rolling Out More RISC-V Infrastructure & Ready-To-Boot Images
AheadComputing Secures $21.5M to Drive RISC-V Innovation for AI and Cloud
Checking Out The RISC V HiFive P550 from SiFive!
Why RISC-V is a viable option for safety-critical applications
Cloud-based RISC-V evaluation platform for sustainable compute
Groundbreaking Formal Verification Further Enhances the Quality of CHERIoT-Ibex
Andes teams on FPGA prototyping for RISC-V developmentAndes Technology has teamed with S2C to develop an FPGA-based prototyping system for its latest RISC-V cores with extensions. The strategic deal uses S2C’s new…
S2C and Andes Technology Collaborating to Accelerate Advanced RISC-V SoC DevelopmentS2C and Andes Technology have unveiled the results of a strategic collaboration designed to significantly enhance FPGA prototyping capabilities for developers of advanced System-on-Chip (SoC)…
Andes Technology and Imagination Technologies Showcase Android 15 on High-Performance RISC-V Based PlatformSan Jose, CA – April 23, 2025 – Andes Technology (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), the leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding…
RISC-V RVA23—A Major MilestoneRISC-V Profiles, including the RVA23 Profile, help accelerate the growth of the RISC-V ecosystem by ensuring compatibility across RISC-V implementations. The 2024 RISC-V Summit North…
RISC-V International Newsletter – April 2025As we wrap up a busy Q1 for RISC-V, the excitement is building as RISC-V Summit Europe 2025 approaches, taking place from May 12-15 in…
Cost-Effective and Scalable: A Smarter Choice for RISC-V DevelopmentThe RISC-V ecosystem is witnessing remarkable growth, driven by increasing industry adoption and a thriving open-source community. As companies and developers seek customizable computing solutions,…
Testing Infineon’s virtual automotive RISC-V chipPLS Programmierbare Logik & Systeme in Germany has added support for the RISC-V open instruction set architecture to test and debug Infineon’s latest automotive processor…
[VIDEO] OpenHW Foundation RISC-V Cores: Empowering the Hardware Revolution for SDVIn this talk, Flo Wohlrab dives deep into the growing impact of industrial-grade, open-source RISC-V cores in the automotive industry, with a spotlight on the…
Canonical Adds the Orange Pi RV2 to Its List of Officially-Supported Ubuntu-Capable RISC-V BoardsCanonical has announced it is adding yet another RISC-V single-board computer to its build list for official Ubuntu Linux operating system images: the recently-released Orange…
Podcast EP282: An Overview of Andes Focus on RISC-V and the Upcoming RISC-V CONDan is joined by Marc Evans, director of business development and technology at Andes. Marc has over twenty years of experience in the use of…
Ubuntu developer images now available for OrangePi RV2: a low-cost RISC-V SBCCanonical, the publisher of Ubuntu, is excited to announce the availability of Ubuntu developer images for the new OrangePi RV2 RISC-V single board computer (SBC). We’re delighted…
Enhancing Commercial Software Adaptation with XuanTie Optimized Computing Libraries (Vectorization)By Zhanheng Yang, Alibaba DAMO Academy 1. Introduction In the previous article of the XuanTie Optimized Computing Libraries series, we provided a systematic overview of…
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World’s First RISC-V Pad with LTE Launched by DeepComputing at RISC-V Summit 2023Author: DeepComputing At the recent RISC-V Summit North America, RISC-V innovation pioneer DeepComputing unveiled their latest product - the world’s first RISC-V Pad which can…
Enabling Secure Open Source ML Products with Open Se CuraAt the recent RISC-V Summit in Santa Clara, Antmicro participated in Google’s announcement of the open source release of project Open Se Cura. The announcement…
Integrating PikeOS with Microchip’s RISC-V based PolarFire® SoC FPGA | PikeOS: A Versatile Hypervisor-RTOSPikeOS, developed by SYSGO GmbH, is a real-time operating system (RTOS) that offers a separation kernel-based hypervisor with multiple partitions for hosting many other operating…
[Case Study] SuperTest – helping TrustInSoft guarantee its customers 100% bug-free source codeSoftware development tool company TrustInSoft, which serves the international aeronautics, telecommunications, industrial IoT, and automotive industries via its offices in Paris (France) and San Francisco…
Quick Time-To-Market with a Compact and Powerful Microchip PolarFire® SoC FPGA System on ModuleThe Mercury+ MP1 System-on-Module: Enclustra’ s Microchip PolarFire SoC FPGA-based module cuts development time from years to months. Mercury+ MP1 from Enclustra offers many advantages…
Accelerating the Open Source Software Ecosystem with RISC-V LabsThe momentum that RISC-V is achieving across the compute spectrum is amazing. Throughout 2023, we have seen RISC-V based computing being applied to every kind…
Debugging RISC-V processors using E-TraceBy: Siemens | Tessent Embedded Analytics | Author: Huw Geddes, Product Manager Debugging RISC-V-based SoCs can be challenging even for devices with only a few…
S2C’s FPGA Prototyping Accelerates Iterations of XiangShan RISC-V ProcessorS2C announced that the Beijing Institute of Open Source Chip (BOSC) adopted its Prodigy S7-19P Logic System, a VU19P-based FPGA prototyping solution, in the development…
RISC-V is Here! RISC-V Summit North America Showcases Innovation, Products, Boards, CommunityMeta, Qualcomm, Red Hat, Synopsys and More Headline Nov. 6-8 Event in Santa Clara, CA RISC-V is here! So is RISC-V Summit North America…
Journeying Beyond AI: Unleashing the Art of VerificationSivakumar P R, Founder and CEO, Maven Silicon, delivered an insightful keynote speech titled 'Journeying Beyond AI: Unleashing the Art of Verification' at the DVCon…
DPI support in Renode for HDL co-simulation with Verilator and QuestaAuthor: Antmicro Hardware Description Languages (HDLs), such as Verilog and SystemVerilog, are used to express the behavior of digital electronic circuits for field-programmable gate arrays…
RISC-V: An Open Standard – Backed by a Global Community – to Enable Open Computing for AllThe entire tech ecosystem benefits from standards being open, whether it’s RISC-V or other popular standards such Ethernet, HTTPS, JPEG, or USB. Three key reasons…
No recent posts listed
World’s First RISC-V Pad with LTE Launched by DeepComputing at RISC-V Summit 2023Author: DeepComputing At the recent RISC-V Summit North America, RISC-V innovation pioneer DeepComputing unveiled their latest product - the world’s first RISC-V Pad which can…
Enabling Secure Open Source ML Products with Open Se CuraAt the recent RISC-V Summit in Santa Clara, Antmicro participated in Google’s announcement of the open source release of project Open Se Cura. The announcement…
Integrating PikeOS with Microchip’s RISC-V based PolarFire® SoC FPGA | PikeOS: A Versatile Hypervisor-RTOSPikeOS, developed by SYSGO GmbH, is a real-time operating system (RTOS) that offers a separation kernel-based hypervisor with multiple partitions for hosting many other operating…
[Case Study] SuperTest – helping TrustInSoft guarantee its customers 100% bug-free source codeSoftware development tool company TrustInSoft, which serves the international aeronautics, telecommunications, industrial IoT, and automotive industries via its offices in Paris (France) and San Francisco…
Quick Time-To-Market with a Compact and Powerful Microchip PolarFire® SoC FPGA System on ModuleThe Mercury+ MP1 System-on-Module: Enclustra’ s Microchip PolarFire SoC FPGA-based module cuts development time from years to months. Mercury+ MP1 from Enclustra offers many advantages…
Accelerating the Open Source Software Ecosystem with RISC-V LabsThe momentum that RISC-V is achieving across the compute spectrum is amazing. Throughout 2023, we have seen RISC-V based computing being applied to every kind…
Debugging RISC-V processors using E-TraceBy: Siemens | Tessent Embedded Analytics | Author: Huw Geddes, Product Manager Debugging RISC-V-based SoCs can be challenging even for devices with only a few…
S2C’s FPGA Prototyping Accelerates Iterations of XiangShan RISC-V ProcessorS2C announced that the Beijing Institute of Open Source Chip (BOSC) adopted its Prodigy S7-19P Logic System, a VU19P-based FPGA prototyping solution, in the development…
RISC-V is Here! RISC-V Summit North America Showcases Innovation, Products, Boards, CommunityMeta, Qualcomm, Red Hat, Synopsys and More Headline Nov. 6-8 Event in Santa Clara, CA RISC-V is here! So is RISC-V Summit North America…
Journeying Beyond AI: Unleashing the Art of VerificationSivakumar P R, Founder and CEO, Maven Silicon, delivered an insightful keynote speech titled 'Journeying Beyond AI: Unleashing the Art of Verification' at the DVCon…
DPI support in Renode for HDL co-simulation with Verilator and QuestaAuthor: Antmicro Hardware Description Languages (HDLs), such as Verilog and SystemVerilog, are used to express the behavior of digital electronic circuits for field-programmable gate arrays…
RISC-V: An Open Standard – Backed by a Global Community – to Enable Open Computing for AllThe entire tech ecosystem benefits from standards being open, whether it’s RISC-V or other popular standards such Ethernet, HTTPS, JPEG, or USB. Three key reasons…
Memory Safety Will Be Key to Tackle Fundamental Cyber SecurityEarlier this month, a U.K. government initiative called Digital Security by Design (DSbD) held a showcase in London to enable companies with pioneering technologies to…
Imagination reveals new power-efficient DXTP GPU for laptops and mobile devicesImagination Technology has announced its newest GPU IP, Imagination DXTP. With 20% improved power efficiency over its predecessor DXT, Imagination brings two new RISC-V GPU models…
Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC VerificationSAN JOSE, Calif., Feb. 20, 2025 (GLOBE NEWSWIRE) -- Breker Verification Systems today confirmed its RISC-V SystemVIP library components and test suite synthesis product portfolio is deployed…
High-schooler creates LinuxPDF: Running Linux on a RISC-V emulator inside a PDF fileA high-schooler who goes by the online handle of ading2210 has released LinuxPDF, software that runs Linux within a PDF file. This comes after his earlier release of DoomPDF,…
The RISC-V Architecture: 16 Boards and MCUs You Should KnowMicrocontrollers are everywhere, powering everything from your dishwasher to powerful computing systems and millions of wearable and IoT devices. For the processor cores and architectures,…
Cortus MINERVA Out-of-Order 4GHz 64-bit RISC-V Processor Platform targets automotive applicationsDate: February 21st, 2025 Location: Mauguio - Montpellier, France Cortus, an innovative fabless semiconductor manufacturing group today announces a key achievement of its high-performance Out-of-Order…
Fedora Rolling Out More RISC-V Infrastructure & Ready-To-Boot ImagesThe Fedora Project is rolling out expanded coverage of RISC-V hardware moving forward and making it easier for those with RISC-V developer boards to run…
AheadComputing Secures $21.5M to Drive RISC-V Innovation for AI and CloudPORTLAND, Ore., Feb. 19, 2025 — AheadComputing today announced it has secured $21.5 million in seed funding to rapidly develop and commercialize its advanced microprocessor architecture designed…
Checking Out The RISC V HiFive P550 from SiFive!Ever wanted to get in on the ground floor of something really cool? Wendell shows you how you can get involved with RISC V development…
Why RISC-V is a viable option for safety-critical applicationsAn intro to RISC-V As safety-critical systems become increasingly complex, the choice of processor architecture plays an important role in ensuring functional safety and system…
Cloud-based RISC-V evaluation platform for sustainable computeUK startup VyperCore is launching a cloud-based evaluation platform for its sustainable RISC-V accelerator chip and chiplet. The VyperLab platform runs on an FPGA in…
Groundbreaking Formal Verification Further Enhances the Quality of CHERIoT-IbexCollaboration milestone addresses key pain points of typical design verification (DV) approaches, improving confidence while reducing cost, time, and resource spend CAMBRIDGE, England – 10th February, 2025 – lowRISC C.I.C.,…