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Ox64 SBC powered by dual RISC-V processors | Giorgio Mendoza, Linux Gizmos
Andes Announces the N25F-SE Processor, the World First RISC-V CPU IP with ISO 26262 Full Compliance | Yahoo! Finance
IAR Systems’ Functional Safety Certified Development Tools for RISC-V support latest SiFive Automotive Solutions | IAR Systems
IAR boosts its automotive RISC-V support | Nick Flaherty, EE News EuropeOx64 SBC powered by dual RISC-V processors | Giorgio Mendoza, Linux Gizmos
Google shows off KataOS, a secure operating system written in Rust | Liam Tung, ZDNETIAR boosts its automotive RISC-V support | Nick Flaherty, EE News EuropeAndes claims first RISC-V CPU IP with full ISO 26262 compliance, plans DSP version | Nick Flaherty, EE News Europe
What Is RISC, What Is RISC V, and How Do They Differ? | Arol Wright, Make Use Of
First RISC-V laptop uses Alibaba TH1520 SoC | Nitin Dahad, EmbeddedFrench secure element processor uses RISC-V | Nick Flaherty, EE News Europe
RISC-V Virtual Prototype | Pieper, P.; Herdt, V.; Drechsler, R., Semiconductor Engineering
Do You Know For Sure Your RISC-V RTL Doesn’t Contain Any Surprises? | Joseph Hupcey III, Semiconductor Engineering
RISC-V CPU Design Courses | Redwood EDA, LLC
Intel May Enable Discrete GPU Driver Development for Arm, RISC-V | Anton Shilov, Tom’s Hardware
Gateway Implementations with RISC-V | Alex Pluemer, Mouser Electronics
Bringing chips back from the dead : MPW-1 Show-off | Sylvain Munaut
Helping to lead the RISC-V revolution | Solid Sands, Electropages
HIPEAC Info Magazine, January 2022 | HIPEAC
Introduction to FPGA Part 12 – RISC-V Custom Peripheral | Shawn Hymel, Digi-Key Electronics
Open source keystroke injector implementation on the Fomu FPGA board | AntmicroDustin: A 16-Cores Parallel Ultra-Low-Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode | Gianmarco Ottavi∗ , Angelo Garofalo∗ , Giuseppe Tagliavini† , Francesco Conti∗ , Alfio Di Mauro‡ , Luca Benini∗‡, and Davide Rossi∗ ∗Department of Electrical, Electronic and Information Engineering (DEI), University of Bologna, Italy †Department of Computer Science and Engineering (DISI), University of Bologna, Italy ‡ IIS Integrated Systems Laboratory, ETH Zurich, Switzerland
WCH CH32V307 RISC-V development board features 8 UART ports controlled over Ethernet | Jean-Luc Aufranc, CNX Software
SmartDV and NSITEXE Sign Agreement to Deploy NSITEXE’s RISC-V 32bit CPU Core throughout North America, China, India, Taiwan | SmartDV
Ox64 SBC powered by dual RISC-V processors | Giorgio Mendoza, Linux GizmosPine64 announced a few days ago their latest SBC based on a dual-core RISC-V processor. The compact Ox64 is enabled with Wi-Fi 4.0, Zigbee BL5.0…
Andes Announces the N25F-SE Processor, the World First RISC-V CPU IP with ISO 26262 Full Compliance | Yahoo! FinanceSystematic failures and random hardware failures can be mitigated by development process and safety designs of the safety-enhanced N25F-SE HSINCHU, TAIWAN, Oct. 17, 2022 (GLOBE…
IAR Systems’ Functional Safety Certified Development Tools for RISC-V support latest SiFive Automotive Solutions | IAR SystemsIAR Embedded Workbench for RISC-V provides full core support for the recently introduced SiFive Automotive E6-A and S7-A products Uppsala, Sweden – October 17, 2022 –…
IAR boosts its automotive RISC-V support | Nick Flaherty, EE News EuropeIAR Systems has added support for the latest RISC-V automotive CPU IP from SiFive to its embedded tools. The IAR Embedded Workbench for RISC-V now…
Ox64 SBC powered by dual RISC-V processors | Giorgio Mendoza, Linux GizmosPine64 announced a few days ago their latest SBC based on a dual-core RISC-V processor. The compact Ox64 is enabled with Wi-Fi 4.0, Zigbee BL5.0…
Google shows off KataOS, a secure operating system written in Rust | Liam Tung, ZDNETSmart devices need better security and Google thinks KataOS, written in the Rust programming language, could help. Google has unveiled KataOS, an early exploration into…
IAR boosts its automotive RISC-V support | Nick Flaherty, EE News EuropeIAR Systems has added support for the latest RISC-V automotive CPU IP from SiFive to its embedded tools. The IAR Embedded Workbench for RISC-V now…
Andes claims first RISC-V CPU IP with full ISO 26262 compliance, plans DSP version | Nick Flaherty, EE News EuropeAndes Technology has launched a safety-enhanced 32bit RISC-V CPU IP that it says is the first to be certified as fully compliant with ISO 26262…
What Is RISC, What Is RISC V, and How Do They Differ? | Arol Wright, Make Use OfWhen talking about processors, x86 and ARM are the two terms that come up the most, especially if we're talking about recent devices. But there…
First RISC-V laptop uses Alibaba TH1520 SoC | Nitin Dahad, EmbeddedEarlier this month RISC-V International announced that ROMA, claimed to be the world’s first native RISC-V development laptop, is powered by Alibaba T-Head’s TH1520 system-on-chip…
French secure element processor uses RISC-V | Nick Flaherty, EE News EuropeFrench processor designer Tiempo Secure has developed secure IP based on the RISC-V open instruction set. The TESIC Secure Element IP uses the RV32IMCB 32bit…
RISC-V Virtual Prototype | Pieper, P.; Herdt, V.; Drechsler, R., Semiconductor EngineeringA new technical paper titled “Advanced Embedded System Modeling and Simulation in an Open Source RISC-V Virtual Prototype” was published by researchers at DFKI GmbH…
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Do You Know For Sure Your RISC-V RTL Doesn’t Contain Any Surprises? | Joseph Hupcey III, Semiconductor EngineeringGiven the relative novelty and complexity of RISC-V RTL designs, whether you are buying a commercially supported core or downloading a popular open-source offering, there…
RISC-V CPU Design Courses | Redwood EDA, LLCThese courses all are made available by Redwood EDA, LLC FREE through June 2022, so enjoy! Computer Architecture is traditionally learned in a university setting…
Intel May Enable Discrete GPU Driver Development for Arm, RISC-V | Anton Shilov, Tom’s HardwareIntel takes aim at Linux enthusiasts with a new initiative. Intel has released request for comments (RFC) patches for its Linux kernel graphics driver enabling…
Gateway Implementations with RISC-V | Alex Pluemer, Mouser ElectronicsReduced instruction-set architectures (ISAs) such as RISC-V provide greater efficiency and less drag on resources than their more complex counterparts. Industrial Internet of Things (IIoT)…
Bringing chips back from the dead : MPW-1 Show-off | Sylvain MunautIn this video I show off the current state of my efforts to bring up the PyFive test chips produced as part of the very…
Helping to lead the RISC-V revolution | Solid Sands, ElectropagesSiFive is creating a new infrastructure to support accelerated ASIC and FPGA design flows, IP delivery, and SoC development. These new developments comprise state-of-the-art compiler…
HIPEAC Info Magazine, January 2022 | HIPEACRead the full edition including RISC-V community member features.
Introduction to FPGA Part 12 – RISC-V Custom Peripheral | Shawn Hymel, Digi-Key ElectronicsA field-programmable gate array (FPGA) is an integrated circuit (IC) that lets you implement custom digital circuits. You can use an FPGA to create optimized…
Open source keystroke injector implementation on the Fomu FPGA board | AntmicroAt Antmicro we work with a large variety of FPGA chips, starting from very large FPGAs we’re using for prototyping ASIC systems, to super small, resource…
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode | Gianmarco Ottavi∗ , Angelo Garofalo∗ , Giuseppe Tagliavini† , Francesco Conti∗ , Alfio Di Mauro‡ , Luca Benini∗‡, and Davide Rossi∗ ∗Department of Electrical, Electronic and Information Engineering (DEI), University of Bologna, Italy †Department of Computer Science and Engineering (DISI), University of Bologna, Italy ‡ IIS Integrated Systems Laboratory, ETH Zurich, SwitzerlandAbstract— Computationally intensive algorithms such as Deep Neural Networks (DNNs) are becoming killer applications for edge devices. Porting heavily data-parallel algorithms on resource-constrained and battery-powered…
WCH CH32V307 RISC-V development board features 8 UART ports controlled over Ethernet | Jean-Luc Aufranc, CNX SoftwareCH32V307V-EVT-R1 is a development board based on WCH CH32V307 RISC-V microcontroller with an Ethernet port, an USB Type-C port, and eight UART interfaces accessible through…
SmartDV and NSITEXE Sign Agreement to Deploy NSITEXE’s RISC-V 32bit CPU Core throughout North America, China, India, Taiwan | SmartDVHigh-Reliability, General-Purpose CPU Based on 32-Bit RISC-V ISA Supports ISO 26262 ASIL D Requirement for Automotive Applications. SmartDV™ Technologies, the leading supplier of Design and…