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VisionFive 2 RISC-V Board Available For Pre-Order | Ian Evenden, Tom’s Hardware
RISC-V International Announces Agenda for RISC-V Summit 2022 | RISC-V International
China may prove Arm wrong about RISC-V’s role in the datacenter | Tobias Mann, The Register
VisionFive 2 RISC-V single-board computer is up for pre-order for $56 and up | Brad Linder, Liliputing
Alibaba T-Head TH1520 RISC-V processor to power the ROMA laptop | Jean-Luc Aufranc, CNX SoftwareAnnouncing RISC-V International’s Expanded Developer Boards Program | RISC-V International
DeepComputing and Xcalibyte announce the ROMA laptop will be powered by TH1520 – the first SoC from Wujian 600’s platform by Alibaba T-Head | Xcalibyte
Dev board for 32bit GigaDevice RISC-V | Steve Bush, Electronics WeeklyLinux 6.0 release – Main changes, Arm, RISC-V, and MIPS architectures | Jean-Luc Aufranc, CNX Software
XuanTie Security System Promotes Rapid Migration of Security Applications from Arm to RISC-V | Vincent Cui, Alibaba CloudSiFive has licenses C++ library for Risc-V | Steve Bush, Electronics Weekly
Researchers Build a RISC-V Chip That Calculates in Posits, Boosting Accuracy for ML Workloads | Gareth Halfacree, Hackster.io
GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors | Nazareno Bruschi∗ , Germain Haugou†‡, Giuseppe Tagliavini∗ , Francesco Conti∗ , Luca Benini∗†, and Davide Rossi∗ (∗University of Bologna, †ETH, ‡GreenWaves-Technologies)SiFive Preps Next-Gen HiFive Unmatched RISC-V Boards | Anton Shilov, Tom’s Hardware
Google Research Releases Circuit Training, an Open-Source Framework for Automated Chip Floorplanning | Gareth Halfacree, AB Open
NSITEXE and Green Hills Software Partner on RISC-V Solutions | Design & ReuseASIC roundup of open source RISC-V CPU cores | Oguz Meteer, BitlogIT
RISC-V SoC + AI – Run a demo of the ncnn inference framework using Allwinner’s D1 “Nezha” Development Board | Verimake
The State of the RISC-V Union, part II | Paul McLellan, Cadence Design Systems
First impression on Nezha RISC-V SBC | 3mdeb
SEGGER J-Link – Performance analysis on RISC-V | SEGGER
At CES2022 Bouffalo Shows its Matter Turnkey Solution | Bouffalo Lab, EE Times
Deep Vision Adopts SiFive RISC-V to Add OpenCV-Enabled AI Support | SiFivePicoclick C3T Is the World’s Smallest IoT Button and It Has a RISC-V Processor | James Lewis, Hackster.io
VisionFive 2 RISC-V Board Available For Pre-Order | Ian Evenden, Tom’s HardwareWith global stocks of Raspberry Pi not being so plentiful, Raspberry Pi alternatives are becoming more and more attractive to makers. StarFive’s VisionFive 2 RISC-V SBC that crowdfunded over…
RISC-V International Announces Agenda for RISC-V Summit 2022 | RISC-V InternationalThis year’s Summit includes keynotes, technical and industry tracks and tutorials, as well as member exhibitions, networking opportunities and more RISC-V International will host…
China may prove Arm wrong about RISC-V’s role in the datacenter | Tobias Mann, The RegisterANALYSIS Arm might not think RISC-V is a threat to its newfound foothold in the datacenter, but growing pressure on Chinese chipmaking could ultimately change that,…
VisionFive 2 RISC-V single-board computer is up for pre-order for $56 and up | Brad Linder, LiliputingThe StarFive VisionFive 2 is a single-board computer with a quad-core RISC-V processor, an integrated GPU, an HDMI 2.0 port with support for 4K video…
Alibaba T-Head TH1520 RISC-V processor to power the ROMA laptop | Jean-Luc Aufranc, CNX SoftwareThe ROMA RISC-V laptop was announced this summer with an unnamed RISC-V processor with GPU and NPU. We now know it will be the Alibaba T-Head TH1520…
Announcing RISC-V International’s Expanded Developer Boards Program | RISC-V InternationalThe RISC-V Developer Boards program drives RISC-V innovation by making development boards more accessible to the global RISC-V community. Read on to learn how the…
DeepComputing and Xcalibyte announce the ROMA laptop will be powered by TH1520 – the first SoC from Wujian 600’s platform by Alibaba T-Head | XcalibyteAlibaba T-Head recently released a brand-new high-performance RISC-V SoC named the TH1520 at The RISC-V Summit China 2022. According to Alibaba “TH1520 demonstrates exceptional speed…
Dev board for 32bit GigaDevice RISC-V | Steve Bush, Electronics WeeklyMikroElektronika has launched a development board for GigaDevice’s GD32VF103VBT6 32bit RISC-V microcontroller in its SiBrain format. Mikroe is the company is behind the ‘Click’ interface…
Linux 6.0 release – Main changes, Arm, RISC-V, and MIPS architectures | Jean-Luc Aufranc, CNX SoftwareSo, as is hopefully clear to everybody, the major version number change is more about me running out of fingers and toes than it is…
XuanTie Security System Promotes Rapid Migration of Security Applications from Arm to RISC-V | Vincent Cui, Alibaba CloudRecently at the RISC-V Summit China 2022 a new high-performance RISC-V-based chip platform named Wujian 600 and the TH1520 chip prototype was revealed. These products…
SiFive has licenses C++ library for Risc-V | Steve Bush, Electronics WeeklyIC intellectual property company SiFive has licensed Segger’s emRun++ C++ library for Risc-V, a library optimised for GCC/LLVM-based tool chains and embedded systems, based on…
Researchers Build a RISC-V Chip That Calculates in Posits, Boosting Accuracy for ML Workloads | Gareth Halfacree, Hackster.ioDesigned as an alternative to floating-point numbers, posits may prove key to boosting machine learning performance. A team of scientists at the Complutense University of…
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GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors | Nazareno Bruschi∗ , Germain Haugou†‡, Giuseppe Tagliavini∗ , Francesco Conti∗ , Luca Benini∗†, and Davide Rossi∗ (∗University of Bologna, †ETH, ‡GreenWaves-Technologies)Abstract—The last few years have seen the emergence of IoT processors: ultra-low power systems-on-chips (SoCs) combining lightweight and flexible micro-controller units (MCUs), often based on…
SiFive Preps Next-Gen HiFive Unmatched RISC-V Boards | Anton Shilov, Tom’s HardwareSiFive is ending production of current-generation Unmatched boards for RISC-V developers. SiFive this week announced that due to challenges with components supply, it would discontinue…
Google Research Releases Circuit Training, an Open-Source Framework for Automated Chip Floorplanning | Gareth Halfacree, AB OpenGoogle Research has released the source code for a chip floor-plan generate based on deep reinforcement learning – after publishing a paper demonstrating how effective…
NSITEXE and Green Hills Software Partner on RISC-V Solutions | Design & ReuseNSITEXE, Inc., a wholly owned subsidiary of Denso Corporation that develops and sells high efficiency processor IP for embedded systems, and Green Hills Software, the…
ASIC roundup of open source RISC-V CPU cores | Oguz Meteer, BitlogITWhile waiting for simulation results for my final paper, I thought I’d synthesize and do place & route of several open source RISC-V CPU cores for fun.…
RISC-V SoC + AI – Run a demo of the ncnn inference framework using Allwinner’s D1 “Nezha” Development Board | VerimakeD1 is Allwinner's first SoC based on the RISC-V ISA,which has a 64-bit Xuantie C906 core from T-Head. The "Nezha" Development Board is an AIoT development board based on the…
The State of the RISC-V Union, part II | Paul McLellan, Cadence Design SystemsThis is part 2 of my post on DAC and RISC-V from December. The first post is here. This post will cover Krste's presentation and then…
First impression on Nezha RISC-V SBC | 3mdebNezha board is a development board that is designed by an AWOL. This project uses a D1 SoC from Allwinner which is used for the…
SEGGER J-Link – Performance analysis on RISC-V | SEGGERWatch how to do a performance analysis on a RISC-V device using SEGGER's market-leading J-Link, Ozone and SystemView to tap into SiFive's insight debug and…
At CES2022 Bouffalo Shows its Matter Turnkey Solution | Bouffalo Lab, EE TimesWith a comprehensive lineup of wireless SOCs, Bouffalo Lab fully supports Matter, the wireless and interoperability standard for smart home devices, offering a complete turnkey…
Deep Vision Adopts SiFive RISC-V to Add OpenCV-Enabled AI Support | SiFiveSiFive, Inc., the founder and leader of RISC-V computing, today announced that Deep Vision will integrate SiFive RISC-V processor IP into its next-generation inference accelerators to enable…
Picoclick C3T Is the World’s Smallest IoT Button and It Has a RISC-V Processor | James Lewis, Hackster.ioProgrammable button supports single, multiple, and long presses while sipping only 3 uA when idle. WiFi-enabled buttons send an MQTT message or REST call from…