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Andes Technology Corp. Announces Its RISC-V CPU IP Serves as the Computing Engine in the New Renesas R9A02G020 MCU ASSP | Andes Technology
First RISC-V chip optimised for motor control | Nick Flaherty, EE News Europe
Renesas extends RISC-V Embedded Processing portfolio | Neil Tyler, New Electronics
RISC-V-Based ASSP EASY – The Start of a New Development Journey | Giancarlo Parodi, RenesasRenesas Extends Leading RISC-V Embedded Processing Portfolio with New Motor Control ASSP Solution | Renesas
NASA, Microchip, SiFive Announces Partnership for RISC-V Spaceflight Computing Platform | Gareth Halfacree, Hackster.io
Renodepedia – From Zephyr’s structured data to traceable and testable open hardware with Renode | Antmicro
NASA has chosen these CPUs to power its next generation of spaceflight computers | Liam Tung, ZD Net
Alibaba Cloud Reveals New RISC-V Development Platform | Robin Mitchell, Electropages
NASA Selects SiFive and Makes RISC-V the Go-to Ecosystem for Future Space Missions | SiFive, Business Wire
SiFive RISC-V CPU cores to power NASA’s next spaceflight computer | Tobias Mann, The Register
SOC Verification Flows and Methodologies | Sivakumar P R, Maven Silicon
Gentoo Linux Packages Up AMD ROCm, Makes Progress On RISC-V, LTO+PGO Python | Michael Larabel, Phoronix
The Chip Shortage, Giant Chips, and the Future of Moore’s Law | Samuel K. Moore, IEEE Spectrum
CH32V307 Chitu Development Board Tutorial: Use CMake to Develop | Yu Fan, VeriMake.io
MiG-V – Made in Germany RISC-V | HENSOLDT
Forces For Change And Competitive Intensity In Semiconductors | Michael Gurau, Forbes
21st Century Cryptography – Asynchronous ASIC | Jason Graalum, Galois
Board with 25 RGB LEDs is offered with ESP32-C3 or ESP32-Pico-D4 | Jean-Luc Aufranc, CNX Software
New Part Day: The RISC-V Lichee-RV Module and Dock | Dave Rowntree, Hackaday
CFU Playground: Full-Stack Open-Source Framework for Tiny Machine Learning (tinyML) Acceleration on FPGAs | Shvetank Prakash∗, Tim Callahan† Joseph Bushagour§, Colby Banbury∗, Alan V. Green†, Pete Warden†, Tim Ansell†, Vijay Janapa Reddi∗, †Google §Purdue University ∗Harvard UniversitySiFive announced new, high performance RISCV cores as AMD is looking for RISCV architect? | René Rebe, Bits inside by René Rebe
When You Reach The Summit, Keep Climbing | Andy Frame, SiFive
Using Imagination Around Arm & RISC-V | Embedded Computing Design Staff, Embedded Computing Design
Andes Technology Corp. Announces Its RISC-V CPU IP Serves as the Computing Engine in the New Renesas R9A02G020 MCU ASSP | Andes TechnologyAndes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International,…
First RISC-V chip optimised for motor control | Nick Flaherty, EE News EuropeRenesas Electronics has developed the industry’s first RISC-V MCU specifically optimized for motor control systems. The R9A02G020 is a pre-programmed application specific standard product (ASSP)…
Renesas extends RISC-V Embedded Processing portfolio | Neil Tyler, New ElectronicsRenesas Electronics has introduced the industry’s first RISC-V MCU specifically optimised for advanced motor control systems. The solution provides customers with a ready-to-use, turnkey solution…
RISC-V-Based ASSP EASY – The Start of a New Development Journey | Giancarlo Parodi, RenesasThe RISC-V instruction set architecture (ISA) is increasingly generating interest and momentum within the embedded community. The free and open RISC ISA is driven by…
Renesas Extends Leading RISC-V Embedded Processing Portfolio with New Motor Control ASSP Solution | RenesasRISC-V based ASSP Offered in Collaboration with Ecosystem Partners Delivers Complete, Production-Ready Motor Control System Solution. Renesas Electronics Corporation (TSE: 6723), a premier supplier of…
NASA, Microchip, SiFive Announces Partnership for RISC-V Spaceflight Computing Platform | Gareth Halfacree, Hackster.ioDesigned to replace existing systems still using a processor design from 1997, the RISC-V-powered chip will offer 100 times the performance. NASA has confirmed a…
Renodepedia – From Zephyr’s structured data to traceable and testable open hardware with Renode | AntmicroThe abundance and diversity of hardware platforms brought about by the growth of ARM, RISC-V and the open software ecosystem presents unprecedented opportunities to product…
NASA has chosen these CPUs to power its next generation of spaceflight computers | Liam Tung, ZD NetNASA selects RISC-V chip designer SiFive to help replace its aging and over-designed spaceflight computers. NASA has selected SiFive, a US chip startup that designs…
Alibaba Cloud Reveals New RISC-V Development Platform | Robin Mitchell, ElectropagesRecently, Chinese giant Alibaba Cloud unveiled a new RISC-V development platform that it hopes will continue to push developers into the field of RISC-V. What…
NASA Selects SiFive and Makes RISC-V the Go-to Ecosystem for Future Space Missions | SiFive, Business WireSiFive X280 delivers 100x increase in computational capability with leading power efficiency, fault tolerance, and compute flexibility to propel next-generation planetary and surface missions. SiFive,…
SiFive RISC-V CPU cores to power NASA’s next spaceflight computer | Tobias Mann, The RegisterAfter more than two decades, the space agency's PowerPC love affair appears to be at an end. Chip designer SiFive said Tuesday its RISC-V-compatible CPU…
SOC Verification Flows and Methodologies | Sivakumar P R, Maven SiliconWe need more and more complex chips and SoCs for all new applications that use the latest technologies like AI. For example, Apple’s 5nm SoC…
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Gentoo Linux Packages Up AMD ROCm, Makes Progress On RISC-V, LTO+PGO Python | Michael Larabel, PhoronixGentoo Linux developers were very busy over the course of 2021 for this popular rolling-release operating system choice. The Gentoo project has published their 2021…
The Chip Shortage, Giant Chips, and the Future of Moore’s Law | Samuel K. Moore, IEEE SpectrumWith COVID-19 shaking the global supply chain like an angry toddler with a box of jelly beans, the average person had to take a crash…
CH32V307 Chitu Development Board Tutorial: Use CMake to Develop | Yu Fan, VeriMake.ioCH32V307 Chitu Development Board Tutorial: Use CMake to Develop Try the tutorial.
MiG-V – Made in Germany RISC-V | HENSOLDTThe HENSOLDT Cyber MiG-V is a general purpose, logic-encrypted processor, Made in Germany, targeting high-security applications. Logic encryption hinders the insertion of hardware Trojans, giving…
Forces For Change And Competitive Intensity In Semiconductors | Michael Gurau, ForbesImportant financial and market forces are creating unprecedented growth and dynamism in the semiconductor industry. The present dynamics include: A worldwide chip shortage impacting industries…
21st Century Cryptography – Asynchronous ASIC | Jason Graalum, GaloisPrior to spinning out of Galois, engineers from Niobium Microsystems completed work on the 21st Century Cryptography DARPA project. This project developed a proof-of-concept ASIC containing high-performance, low-energy, side-channel…
Board with 25 RGB LEDs is offered with ESP32-C3 or ESP32-Pico-D4 | Jean-Luc Aufranc, CNX SoftwareIn case you are in need of a tiny WiFI or Bluetooth-connected board with an RGB LED matrix, two have shown up on Banggood with…
New Part Day: The RISC-V Lichee-RV Module and Dock | Dave Rowntree, HackadaySipeed have been busy leveraging developments in the RISC-V arena, with an interesting, low-cost module they call the Lichee RV. It is based around the Aliwinner D1…
CFU Playground: Full-Stack Open-Source Framework for Tiny Machine Learning (tinyML) Acceleration on FPGAs | Shvetank Prakash∗, Tim Callahan† Joseph Bushagour§, Colby Banbury∗, Alan V. Green†, Pete Warden†, Tim Ansell†, Vijay Janapa Reddi∗, †Google §Purdue University ∗Harvard UniversityAbstract: We present CFU Playground, a full-stack open-source framework that enables rapid and iterative design of machine learning (ML) accelerators for embedded ML systems. Our…
SiFive announced new, high performance RISCV cores as AMD is looking for RISCV architect? | René Rebe, Bits inside by René Rebe#SiFive p650 high performance #RISCV cores w/ Vector and Hypervisor extension while AMD is hiring RISCV engineers, too?! Watch the full video.
When You Reach The Summit, Keep Climbing | Andy Frame, SiFiveThe RISC-V Summit 2021 highlighted to the world that the future of RISC-V has no limits! 2021 has been an outstanding year for SiFive, and…
Using Imagination Around Arm & RISC-V | Embedded Computing Design Staff, Embedded Computing DesignChampions of the open-standard ISA expect it to start displacing competitive offerings en masse over the next few years. While that remains to be seen,…