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RISC-V Compressed Instructions for SERV | Abdul Wadood, LFX Mentorship at RISC-V InternationalEverything RISC-V at the Design Automation Conference! | RISC-V International
Imperas announces the latest updates to RVVI and welcomes the adoption by many leading RISC V processor developers | Imperas Software
Open Standard RISC-V Verification Interface (RVVI) for SOC testing | Nick Flaherty, EE News Europe
China pins hopes on local RISC-V start-ups to crack Western monopoly on CPU chips | Che Pan, South China Morning Post
Progress in Porting Android onto RISC-V: Android 12 upgrade, vendor modules and TensorFlow Lite | Mao Han, Alibaba Cloud
ISA Extension For Low-Precision NN Training On RISC-V Cores | Luca Bertaccini, Gianna Paulin, Tim Fischer, Stefan Mach, Luca Benini, Semiconductor EngineeringEurope steps up as RISC-V ships 10bn cores | Nick Flaherty, EE News Europe
RISC-V Opens the Door on 48-bit Computing | Agam Shah, HPC Wire
Imperas and Breker partner for Risc-V system-level verification | Steve Bush, Electronics Weekly
First RISC-V-Based SoC FPGA Enters Mass Production | Microchip Technology, EE Time Asia
SiFive arrives in Cambridge to hire 100 for ascendant RISC-V computing | Mike Scialom, Cambridge Independent
Build an open source-hardware Allwinner D1s RISC-V Linux SBC for under $10 | Jean-Luc Aufranc, CNX Software
Tiny SBC runs Linux on new RAM-equipped Allwinner RISC-V SoC |
SME: Scalable Masking Extensions | Ben Marshall (PQShield Ltd and University of Bristol) and Dan Page (University of Bristol)Sneak peek into SiFive’s most powerful RISC-V yet | Steve Bush, Electronics Weekly
Video: 5 Stage Pipeline: RISC-V Processor In TS (part 3) | Low Level JavaScript
Codasip boosts Studio processor design tools | Neil Tyler, New Electronics
RISC-V-Based VEGA Brings Continual Learning to TinyML with an Order of Magnitude Efficiency Gain | Gareth Halfacree, Hackster.ioMangoPi-MQ1 Is an Ultra-Compact, Soon-to-be-Open Source Allwinner D1 RISC-V Dev Board | Gareth Halfacree, Hackster.io
New Allwinner RISC-V Chip Uncovered on Tiny Board | Ian Evenden, Tom’s Hardware
Kit Close-Up: Lattice Semiconductor’s Crosslink-NX Development Kit | William G. Wong, Electronic Design
Socionext, Techsor and ZiFiSense Unveil IC for “ZETag,” a New Cloud Tag to Utilize ZETA Communication | AI Technology Insights
Intel CTO Greg Lavender interview — Why chip maker is spending on both manufacturing and software | Dean Takahashi, Venture Beat
RISC-V Compressed Instructions for SERV | Abdul Wadood, LFX Mentorship at RISC-V InternationalIn Spring 2022, various mentorship projects were offered by RISC-V International on the LFX platform of the Linux Foundation. I got selected for one of…
Everything RISC-V at the Design Automation Conference! | RISC-V InternationalThe Design Automation Conference is here and we're thrilled to share look at all the RISC-V happenings during the show. If you are interested in…
Imperas announces the latest updates to RVVI and welcomes the adoption by many leading RISC V processor developers | Imperas SoftwareImperas Software Ltd., the leader in RISC-V simulation solutions, today announced the latest updates for RVVI (RISC-V Verification Interface) for RISC-V processor verification with virtual peripherals to support asynchronous…
Open Standard RISC-V Verification Interface (RVVI) for SOC testing | Nick Flaherty, EE News EuropeImperas Software in the UK has extended the RVVI (RISC-V Verification Interface) with virtual peripherals to support asynchronous events and system level interrupts. RVVI is an…
China pins hopes on local RISC-V start-ups to crack Western monopoly on CPU chips | Che Pan, South China Morning PostChina is seeing a chance to improve its self sufficiency in microprocessors, the heart of every smart device, through the open-standard RISC-V chip design architecture,…
Progress in Porting Android onto RISC-V: Android 12 upgrade, vendor modules and TensorFlow Lite | Mao Han, Alibaba CloudLast year Alibaba T-Head reported that the basic features of Android had been ported onto RISC-V-based Xuantie cores. Since then more effort has been spent…
ISA Extension For Low-Precision NN Training On RISC-V Cores | Luca Bertaccini, Gianna Paulin, Tim Fischer, Stefan Mach, Luca Benini, Semiconductor EngineeringAbstract “Low-precision formats have recently driven major breakthroughs in neural network (NN) training and inference by reducing the memory footprint of the NN models and…
Europe steps up as RISC-V ships 10bn cores | Nick Flaherty, EE News EuropeIt may come as a surprise that over 10 billion RISC-V processor cores have shipped. After all, it took ARM 17 years to reach that…
RISC-V Opens the Door on 48-bit Computing | Agam Shah, HPC WireThere’s a growing interest among silicon providers backing RISC-V to introduce 48-bit computing in custom chips to meet their specific requirements. The 48-bit long instructions…
Imperas and Breker partner for Risc-V system-level verification | Steve Bush, Electronics WeeklyRISC-V simulation company Imperas Software has announced a partnership with Breker Verification Systems, a provider of test content synthesis for verification environments, to develop interfaces…
First RISC-V-Based SoC FPGA Enters Mass Production | Microchip Technology, EE Time AsiaThe first SoC field programmable gate array (FPGA) to support the royalty-free RISC-V open Instruction Set Architecture (ISA) has entered volume production, marking a major…
SiFive arrives in Cambridge to hire 100 for ascendant RISC-V computing | Mike Scialom, Cambridge IndependentSiFive, the California-based founder and leader of RISC-V computing, has opened its new UK Research & Development (R&D) Centre at WeWork on Station Road –…
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Build an open source-hardware Allwinner D1s RISC-V Linux SBC for under $10 | Jean-Luc Aufranc, CNX SoftwareWe covered Allwinner D1s RISC-V processor with 64MB built-in RAM a few days ago, and we’ve just found out about Xassette-Asterisk, an open-source hardware board…
Tiny SBC runs Linux on new RAM-equipped Allwinner RISC-V SoC |MangoPi is prepping a tiny “MangoPi-MQ1” SBC with the new Allwinner F133-A (D1s), a spin-down of Allwinner’s D1 that adds 64MB RAM. Both SoCs use…
SME: Scalable Masking Extensions | Ben Marshall (PQShield Ltd and University of Bristol) and Dan Page (University of Bristol)Supporting masking countermeasures for non-invasive side-channel security in instructions set architectures is a hard problem. Masked operations often have a large number of inputs and…
Sneak peek into SiFive’s most powerful RISC-V yet | Steve Bush, Electronics WeeklySo far only called ‘Next Generation Core’ or Next-Gen, its official name, final design specs and availability will be unveiled early in December at the…
Video: 5 Stage Pipeline: RISC-V Processor In TS (part 3) | Low Level JavaScriptRISC-V CPU in TypeScript: Emulator Watch the full video.
Codasip boosts Studio processor design tools | Neil Tyler, New ElectronicsCodasip, a supplier of customisable RISC-V processor IP and tools, has announced further enhancements to its Studio processor design toolset. New features in Studio 9.1…
RISC-V-Based VEGA Brings Continual Learning to TinyML with an Order of Magnitude Efficiency Gain | Gareth Halfacree, Hackster.ioBased on the PULP Platform, this RISC-V chip could offer hundreds of thousands of hours of operation on a single battery charge. A team of…
MangoPi-MQ1 Is an Ultra-Compact, Soon-to-be-Open Source Allwinner D1 RISC-V Dev Board | Gareth Halfacree, Hackster.ioSingle-board computer startup MangoPi has shown off prototypes of a low-cost development board based on the recently-open sourced XuanTie C906 RISC-V core — and promises…
New Allwinner RISC-V Chip Uncovered on Tiny Board | Ian Evenden, Tom’s HardwareReduced instruction set, reduced size. A new version of the Allwinner D1 RISC-V media board has come to light (via CNX Software). The D1s, also…
Kit Close-Up: Lattice Semiconductor’s Crosslink-NX Development Kit | William G. Wong, Electronic DesignEditor Bill Wong examines the board and the software tools available for FPGA development. It supports a range of soft core processors including RISC-V. The…
Socionext, Techsor and ZiFiSense Unveil IC for “ZETag,” a New Cloud Tag to Utilize ZETA Communication | AI Technology InsightsSocionext Inc., ZiFiSense and Techsor announced that the companies have jointly developed a new IC “SC1330,” designed for ZETag, a next generation Cloud Tag that…
Intel CTO Greg Lavender interview — Why chip maker is spending on both manufacturing and software | Dean Takahashi, Venture BeatIntel has been on a spending spree ever since Pat Gelsinger returned to the company as CEO earlier this year. He pledged to spend $20…