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Elektor Engineering Insights #3 – RISC-V | Stuart Cording, Elektor TV
Co-developing Machine Learning with a RISC-V vector core using Renode for Google Research | Antmicro
Ventana Micro CEO explains next gen data centers are driven by RISC-V and open standards | Ventana Micro Systems
Ferrous Systems and Espressif’s Rust Training on ESP32 | Espressif
Imagination unveils IMG RTXM-2200 32-bit RISC-V real-time “Catapult” CPU | Jean-Luc Aufranc, CNX Software
Ubuntu Working To Provide Good Support For The VisionFive Low-Cost RISC-V Board | Michael Larabel, Phoronix
StarFive Survey Announced | StarFive
RISC-V Ratifies New Specifications, Including a “Cheap” Multiply-Only Operation for MCUs and FPGAs | Gareth Halfacree, Hackster.ioLichee RV-86 RISC-V Linux 4-inch panel targets home automation, HMI applications | Jean-Luc Aufranc, CNX Software
CAP-VMs: Capability-Based Isolation and Sharing for Microservices | Vasily A. Sartakov, Lluís Vilanova, David Eyers, Takahiro Shinagawa, Peter Pietzuchnews Introducing ESP32-C5: Espressif’s first Dual-Band Wi-Fi 6 MCU | Espressif
FREE Trial of Beetle ESP32 – C3 | DFRobot
The 5th AI Edge Contest (Implementation Contest 3) Vehicle Driving Image Recognition using RISC-V | Signate
2nd National RISC-V Student Contest 2021-2022 Sponsored by Thales, the GDR SOC2 and the CNFM | Thales
Open Source Debayerization blocks in FPGA | Antmicro
Enthusiasts dash for RISC-V computer with GPU | Agam Shah, The Register
“Una versión de Windows para RISC-V es posible”: hablamos con Roger Espasa, CEO de Semidynamics | Javier Pastor, Xataka
Green Hills covers RISC-V with Integrity | Steve Bush, Electronics Weekly
Vortex: Extending the RISC-V ISA for GPGPU and 3D-Graphics Research | Blaise Tine, Fares Elsabbagh, Krishna Yalamarthy, and Hyesoon Kim, Georgia Institute of Technology
RISC-V: The Next Revolution in the Open Hardware Movement | Olivier Lambert, The New Stack
Getting Started with the Yocto Linux BSP for Polarfire SoC FPGA Icicle Kit | Jean-Luc Aufranc, CNX Software
Dev kit debuts RISC-V XuanTie C910 SoC with a 3D GPU and Android and Linux support | Eric Brown, Linux Gizmos
Elektor Engineering Insights #3 – RISC-V | Stuart Cording, Elektor TVWhat's all this #RISCV stuff about? We spoke to Martin Croome of GreenWaves Technologies and Simon Davidmann from Imperas Software to understand. Watch the full…
Co-developing Machine Learning with a RISC-V vector core using Renode for Google Research | AntmicroThe landscape of Machine Learning software libraries and models is evolving rapidly, and to satisfy the ever-increasing demand for memory and compute while managing latency,…
Ventana Micro CEO explains next gen data centers are driven by RISC-V and open standards | Ventana Micro SystemsNext generation data center architectures are being driven by RISC-V and open standards. At the The Six Five Summit (www.thesixfivesummit.com) Ventana founder and CEO Balaji…
Ferrous Systems and Espressif’s Rust Training on ESP32 | EspressifRust is currently becoming popular in embedded systems, and the support for ESP32 is being developed by Espressif and the ESP-RS community. To consolidate this…
Imagination unveils IMG RTXM-2200 32-bit RISC-V real-time “Catapult” CPU | Jean-Luc Aufranc, CNX SoftwareImagination IMG RTXM-2200 32-bit RISC-V real-time CPU core is the first member of the company’s Catapult family comprised of four distinct RISC-V families for dynamic…
Ubuntu Working To Provide Good Support For The VisionFive Low-Cost RISC-V Board | Michael Larabel, PhoronixIn recent weeks Ubuntu developers have been working on bringing up and improving support for the Starfive VisionFive, which is one of the most promising…
StarFive Survey Announced | StarFiveBased on RISC-V ultra-high performance 8-core SoC, what end product do you want? If a RISC-V SoC could be comparable to an 8-core ARM SoC…
RISC-V Ratifies New Specifications, Including a “Cheap” Multiply-Only Operation for MCUs and FPGAs | Gareth Halfacree, Hackster.ioRISC-V International has announced a new batch of specifications detailing extensions and standards, which can be added to the RISC-V instruction set architecture — the…
Lichee RV-86 RISC-V Linux 4-inch panel targets home automation, HMI applications | Jean-Luc Aufranc, CNX SoftwareWhen Sipeed first introduced the Lichee RV module with Allwinner D1 RISC-V SoC last November, they also teased the Lichee RV-86, an “86 Box” with…
CAP-VMs: Capability-Based Isolation and Sharing for Microservices | Vasily A. Sartakov, Lluís Vilanova, David Eyers, Takahiro Shinagawa, Peter PietzuchCloud stacks must isolate application components, while permitting efficient data sharing between components deployed on the same physical host. Traditionally, the MMU enforces isolation and…
news Introducing ESP32-C5: Espressif’s first Dual-Band Wi-Fi 6 MCU | EspressifEspressif’s ESP32-C5 is the industry’s first RISC-V SoC solution that supports 2.4 and 5 GHz dual-band Wi-Fi 6, along with Bluetooth LE. It is designed…
FREE Trial of Beetle ESP32 – C3 | DFRobotGet a FREE Trial of Beetle ESP32 - C3 Thank you for your interest in this Free Trial. DFRobot has always been working to provide…
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The 5th AI Edge Contest (Implementation Contest 3) Vehicle Driving Image Recognition using RISC-V | SignateWith the progress of artificial intelligence (AI) technology, social implementation such as image recognition using AI technology, automatic driving, and natural language processing is rapidly…
2nd National RISC-V Student Contest 2021-2022 Sponsored by Thales, the GDR SOC2 and the CNFM | ThalesYou are students and like new challenges. You are interested in electronics and computer architectures and want to participate in the design of a renowned…
Open Source Debayerization blocks in FPGA | AntmicroIn modern digital camera systems, the captured image undergoes a complex process involving various image signal processing (ISP) techniques to reproduce the observed scene as…
Enthusiasts dash for RISC-V computer with GPU | Agam Shah, The RegisterIt seems computers without an Arm or x86 chip are in serious demand in the RISC-V community. A Raspberry Pi-like small-board computer with an RISC-V…
“Una versión de Windows para RISC-V es posible”: hablamos con Roger Espasa, CEO de Semidynamics | Javier Pastor, XatakaNo ocurre todos los días que Europa lance un chip propio. Lo hicieron estos días con el EPAC1.0, un SoC que destacaba por utilizar la…
Green Hills covers RISC-V with Integrity | Steve Bush, Electronics WeeklyGreen Hills Software has announced a version of its safety and security-enhanced Integrity real-time operating system for RISC-V. The RTOS is integrated with hardware boards…
Vortex: Extending the RISC-V ISA for GPGPU and 3D-Graphics Research | Blaise Tine, Fares Elsabbagh, Krishna Yalamarthy, and Hyesoon Kim, Georgia Institute of TechnologyThe importance of open-source hardware and software has been increasing. However, despite GPUs being one of the more popular accelerators across various applications, there is…
RISC-V: The Next Revolution in the Open Hardware Movement | Olivier Lambert, The New StackRISC-V is an open standard instruction-set architecture for computer chips. RISC stands for “reduced instruction set computer.” Lately, this project has attracted a lot of…
Getting Started with the Yocto Linux BSP for Polarfire SoC FPGA Icicle Kit | Jean-Luc Aufranc, CNX SoftwareLast month I received Microchip PolarFire SoC FPGA Icicle development kit that features PolarFire SoC FPGA with a Penta–core 64-bit RISC-V CPU subsystem and an FPGA with…
Dev kit debuts RISC-V XuanTie C910 SoC with a 3D GPU and Android and Linux support | Eric Brown, Linux GizmosSipeed and Alibaba T-Head have opened $399 pre-orders on an “RVB-ICE” dev kit featuring a RISC-V compatible, dual-core, 1.2GHz XuanTie C910 ICE SoC with a…