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RISC-V Vector Processing is Taking Off | SiFive
GreenWaves will Demonstrate Live the Ground-breaking AI and DSP Demos on its Ultra Low Power Chip at Embedded World 2022 | GreenWaves Technologies
Overtake the Competition in Automotive Design with RISC-V Innovations | Codasip
RISC-V Announces First New Specifications of 2022, Adding to 16 Ratified in 2021 | RISC-V International
Build an IoT App with Zig and LoRaWAN | Lee Lup Yuen, Mr. Tech Blog
OpenHW Group announces RISC-V-based CORE-V MCU development kit | Nitin Dahad, Embedded.com
Hardware Dynamic IFT Mechanism That Scales to Complex Open-Source RISC-V Processors | Semiconductor Engineering
Think Silicon NEOX RISC-V GPU offers 3D graphics or AI acceleration | Jean-Luc Aufranc, CNX Software
Siemens streamlines, secures embedded RISC-V development with latest Nucleus ReadyStart solution | Siemens
QWERTY’s ICE-V Wireless Packs RISC-V, FPGA, Bluetooth, and Wi-Fi Into a Single Handy Board | Gareth Halfacree, Hackster.io
Renode 1.13 for improved machine learning and pre-silicon development | Antmicro
RISC-V Upstart Targets ML Inference Performance, Power Efficiency | Jeffrey Burt, The Next Platform
6,000 RISC-V Cores on a Xilinx FPGA Break the CoreScore World Record | Francisco Pires, Tom’s Hardware
Chiplet Strategy is Key to Addressing Compute Density Challenges | Balaji Baktha of Ventana Micro Systems, EE Times
Bluespec, Inc. Releases Ultra-Low Footprint RISC-V Processor Family for Xilinx FPGAs, Offers Free Quick-Start Evaluation | Design & Reuse
VS Code Venus RISC-V extension 1.0.0 released | Stefan Wallentowitz, RISC-V @ HM
Maven Silicon organized a Panel Discussion on the topic “Hard-to-Hire VLSI Engineers”
Codasip Opens UK Design Center Led by Simon Bewick | Codasip
RISC-V – running GNOME OS on SiFive hardware for the first time | Valentin David and Sam Thursfield, Codethink
SHREC Students Clinch Best Paper Award for Research in Space Computing | Leah Russell,New CoreScore World Record Crams 6,000 SERV RISC-V Cores Into a Single FPGA | Gareth Halfacree, Hackster.io
Studying RISC-V architecture to create customized systems for space computing | Leah Russell, University of PittsburghEdgeQ Samples 5G Basestation-on-a-Chip | Sally Ward-Foxton, EE Times
RISC-V Vector Processing is Taking Off | SiFiveThe RISC-V Vector Extension (RVV) Version 1.0 was ratified by RISC-V International in 2021. Since this public debut, there has been growing excitement about vector…
GreenWaves will Demonstrate Live the Ground-breaking AI and DSP Demos on its Ultra Low Power Chip at Embedded World 2022 | GreenWaves TechnologiesLocated in the micro-and nano-electronics hotspot of Grenoble, GreenWaves is a fabless semiconductor startup that designs and brings to market advanced ultra-low-power AI and DSP…
Overtake the Competition in Automotive Design with RISC-V Innovations | CodasipIn conversation with Jamie Broome, Codasip VP of Automotive Jamie Broome recently joined Codasip as VP Automotive with more than 20 years of semiconductor…
RISC-V Announces First New Specifications of 2022, Adding to 16 Ratified in 2021 | RISC-V InternationalEfficient Trace, Supervisor Binary Interface, Unified Extensible Firmware Interface, and Zmmul Multiply-Only Extension Accelerate Embedded- and Large-System Design. Six Additional Specifications Already In the Pipeline…
Build an IoT App with Zig and LoRaWAN | Lee Lup Yuen, Mr. Tech BlogSee the full tutorial and instructions.
OpenHW Group announces RISC-V-based CORE-V MCU development kit | Nitin Dahad, Embedded.comThe OpenHW Group has announced a comprehensive open- source RISC-V microcontroller (MCU) development kit for embedded internet of things (IoT), and artificial intelligence (AI) driven…
Hardware Dynamic IFT Mechanism That Scales to Complex Open-Source RISC-V Processors | Semiconductor EngineeringNew technical paper titled “CellIFT: Leveraging Cells for Scalable and Precise Dynamic Information Flow Tracking in Hardware Designs” by researchers at ETH Zurich and Intel. …
Think Silicon NEOX RISC-V GPU offers 3D graphics or AI acceleration | Jean-Luc Aufranc, CNX SoftwareThink Silicon NEOX GPU family with models optimized for graphics (NEOX|G) or artificial intelligence (NEOX|A) is based on the RISC-V RV64C ISA instruction set with…
Siemens streamlines, secures embedded RISC-V development with latest Nucleus ReadyStart solution | SiemensSiemens Digital Industries Software announced today availability of its leading Nucleus™ ReadyStart™ solution for embedded development targeting the fast-growing adoption of the RISC-V architecture. Building…
QWERTY’s ICE-V Wireless Packs RISC-V, FPGA, Bluetooth, and Wi-Fi Into a Single Handy Board | Gareth Halfacree, Hackster.ioThe ICE-V Wireless crowdfunding campaign is now live, with 250 units available at $75 plus shipping each. Backers ordering the low-cost FPGA development board during…
Renode 1.13 for improved machine learning and pre-silicon development | AntmicroAfter a longer while, we are excited to announce that the next release of Renode is here. Since the previous release we’ve been busy working with many…
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RISC-V Upstart Targets ML Inference Performance, Power Efficiency | Jeffrey Burt, The Next PlatformThere is a growing number of vendors big and small going hard to the hoop to make processors for artificial intelligence workloads. AI and machine…
6,000 RISC-V Cores on a Xilinx FPGA Break the CoreScore World Record | Francisco Pires, Tom’s HardwareA new world record for the densest arrangement of RISC-V cores (measured by the CoreScore benchmark) has been achieved by pairing 6,000 RISC-V SERV cores…
Chiplet Strategy is Key to Addressing Compute Density Challenges | Balaji Baktha of Ventana Micro Systems, EE TimesData center workloads are quickly evolving, demanding high compute density with varying mixes of compute, memory and IO capability. This is driving architectures that are…
Bluespec, Inc. Releases Ultra-Low Footprint RISC-V Processor Family for Xilinx FPGAs, Offers Free Quick-Start Evaluation | Design & ReuseBluespec, Inc., a founding member of RISC-V International and supplier of RISC-V Processor IP and tools, released the MCU RISC-V processor family targeted at ultra-low…
VS Code Venus RISC-V extension 1.0.0 released | Stefan Wallentowitz, RISC-V @ HMWe have released the first public stable version of our VS Code extension that is based on the RISC-V extension. You only need this extension…
Maven Silicon organized a Panel Discussion on the topic “Hard-to-Hire VLSI Engineers”The semiconductor industry experts shared their perspectives on hiring and upskilling the VLSI engineers in this insightful panel discussion organized by Maven Silicon. In this…
Codasip Opens UK Design Center Led by Simon Bewick | CodasipRead the full announcement. OVER ONE HUNDRED ENGINEERS TO BE HIRED IN MULTIPLE LOCATIONS Codasip, the leading supplier of customizable RISC-V processor IP, announced today…
RISC-V – running GNOME OS on SiFive hardware for the first time | Valentin David and Sam Thursfield, CodethinkWe continue to participate in the promising RISC-V ecosystem. Already in 2021, Ben Dooks fixed a challenging kernel bug, Robin Heywood prototyped an Arduino Mini…
SHREC Students Clinch Best Paper Award for Research in Space Computing | Leah Russell,When choosing a processor for space computing, there are many factors that come into play: because of the rigors of a harsh environment, developers must…
New CoreScore World Record Crams 6,000 SERV RISC-V Cores Into a Single FPGA | Gareth Halfacree, Hackster.ioA single high-end Xilinx FPGA has played host to an impressive 6,000 individual SERV cores — a new CoreScore world record. There's a new world…
Studying RISC-V architecture to create customized systems for space computing | Leah Russell, University of PittsburghWhen choosing a processor for space computing, there are many factors that come into play: because of the rigors of a harsh environment, developers must…
EdgeQ Samples 5G Basestation-on-a-Chip | Sally Ward-Foxton, EE TimesEdgeQ, the startup making basestation-on-a-chip silicon and software for 5G deployments, is now sampling its chip and phy software. The company has also released a…