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HiPEAC Info Issue 66 | HiPEAC
Accelerating ML Recommendation With Over 1,000 RISC-V/Tensor Processors on Esperanto’s ET-SoC-1 Chip | David R. Ditzel, Esperanto Technologies
Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on a 7nm Chip | Stanford Online
Experimental evaluation of neutron-induced errors on a multicore RISC-V platform | Fernando Fernandes dos Santos (TARAN), Angeliki Kritikakou (TARAN), Olivier Sentieys (TARAN)
Thermal (IR) Imaging Pipeline (ISP) Core on PolarFire® SoC FPGA SoM | Microchip
First RISC-V 3D GPUs Will Be Demoed Next Week | Mark Tyson, Tom’s Hardware
An Introduction to RISC-V—Understanding RISC’s Open ISA | Eduardo Corpeño, All About Circuits
Think Silicon to Unveil Industry’s First RISC-V 3D GPU at Embedded World 2022 | Think Silicon, Yahoo! Finance
Codasip appoints Mike Eftimakis as VP of Strategy and Ecosystem | Codasip
XuanTie C906 Tops MLPerf Tiny v0.7 Benchmark | MengChang, Alibaba Cloud
L’ESP32-C5 est la première puce-système RISC-V qui prend en charge le Wi-Fi 6 bibande et le Bluetooth LE | Pierrick Arlot, L’embarque.
EPI EPAC1.0 RISC-V Test Chip Samples Delivered | European Processor Initiative
Global alliance formed to promote open hardware support for women and underrepresented individuals | Aimee Kalnoskas, EE World Online
Video: RISC-V RV32I B-Type | Maven Silicon
PUFiot: An Essential Secure Coprocessor for RISC-V | Sam Chung, Sean H. Wu, and Evans Yang, PUF Security
Video: It’s Not Just About Embedded! | The Yocto Project
Zephyr RTOS + RISC-V – see the live demo at Open Source Summit/Embedded Linux Conference! | Jonathan Beri, Golioth
New release of SweRVolf RISC-V SoC project aims for lower barrier to entry | Gareth Halfacree, The Register
Optimization Driving Changes In Microarchitectures | Ann Steffora Mutschler, Semiconductor Engineering
RISC-V Chiplets, Disaggregated Die, and Tiles | Chris Jones, SiFive
ZAYA now supports RISC-V | Zaya
Open source SystemVerilog tools in ASIC design | Antmicro, Google Open Source Blog
Unlock the RISC-V Naming Code | Richard A. Quinnell, Digi-Key
HiPEAC Info Issue 66 | HiPEACThanks to a wealth of industry support, RISC-V International is becoming ever stronger: ‘Many large companies have joined the foundation, meaning that no single company…
Accelerating ML Recommendation With Over 1,000 RISC-V/Tensor Processors on Esperanto’s ET-SoC-1 Chip | David R. Ditzel, Esperanto TechnologiesMachine learning (ML) recommendation workloads have demanding performance and memory requirements and, to date, have largely been run on servers with x86 processors. To accelerate…
Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on a 7nm Chip | Stanford OnlineTo accelerate Machine Learning Recommendation and other workloads, Esperanto Technologies has implemented over a thousand low-power RISC-V processors on a single chip along with a…
Experimental evaluation of neutron-induced errors on a multicore RISC-V platform | Fernando Fernandes dos Santos (TARAN), Angeliki Kritikakou (TARAN), Olivier Sentieys (TARAN)RISC-V architectures have gained importance in the last years due to their flexibility and open-source Instruction Set Architecture (ISA), allowing developers to efficiently adopt RISC-V…
Thermal (IR) Imaging Pipeline (ISP) Core on PolarFire® SoC FPGA SoM | MicrochipOur Mi-V partner, Digital Core Technologies (DCT), has developed a thermal Imaging Pipeline on PolarFire® SoC FPGA. The thermal Image Signal Processor (ISP) is an…
First RISC-V 3D GPUs Will Be Demoed Next Week | Mark Tyson, Tom’s HardwareWe often hear about RISC-V, its competitive open-source architecture, and how it is making inroads into the CPU industry. However, last year we reported on…
An Introduction to RISC-V—Understanding RISC’s Open ISA | Eduardo Corpeño, All About CircuitsThis article is a primer into the basics of RISC-V. The open architecture philosophy is exposed, along with a technical description of the modular ISA,…
Think Silicon to Unveil Industry’s First RISC-V 3D GPU at Embedded World 2022 | Think Silicon, Yahoo! FinanceThink Silicon®, a leader in ultra-low power graphics IP, will showcase the industry’s first RISC-V-based GPU – the NEOX™ G-Series & A-Series – at Embedded…
Codasip appoints Mike Eftimakis as VP of Strategy and Ecosystem | CodasipCodasip, the leader in customizable RISC-V processor IP, today announced it has appointed Mike Eftimakis as VP Strategy and Ecosystem. Mike Eftimakis has an extensive…
XuanTie C906 Tops MLPerf Tiny v0.7 Benchmark | MengChang, Alibaba CloudXuanTie C906 is a processor developed by Alibaba Cloud based on the RISC-V instruction set architecture. It has attained top marks in the most recent…
L’ESP32-C5 est la première puce-système RISC-V qui prend en charge le Wi-Fi 6 bibande et le Bluetooth LE | Pierrick Arlot, L’embarque.Connue pour ses puces-systèmes ESP32 compatibles Wi-Fi, Bluetooth et Bluetooth Low Energy et très présente sur le marché des objets connectés, la société Espressif Systems…
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EPI EPAC1.0 RISC-V Test Chip Samples Delivered | European Processor InitiativeAnother step closer to demonstrate the capabilities of a RISC-V based European microprocessor. The European Processor Initiative (EPI) https://www.european-processor-initiative.eu/, a project with 28 partners from…
Global alliance formed to promote open hardware support for women and underrepresented individuals | Aimee Kalnoskas, EE World OnlineRISC-V International, a global open hardware standards organization, today announced the launch of the Open Hardware Diversity Alliance. The global Alliance, created by CHIPS Alliance,…
Video: RISC-V RV32I B-Type | Maven SiliconThis video explains the RV32I B-Type instructions. To know more, explore our RISC-V courses, https://elearn.maven-silicon.com/risc-v RISC-V is growing rapidly, follow this RISC-V video…
PUFiot: An Essential Secure Coprocessor for RISC-V | Sam Chung, Sean H. Wu, and Evans Yang, PUF SecurityThe number of connected IoT devices exceeded 46 billion in 2021 and is expected to reach a remarkable 125 billion by 2030. This will shift…
Video: It’s Not Just About Embedded! | The Yocto Project“Embedded Linux people build custom Linux systems.” Thats how things are, right? And yeah, they do that a real lot for sure. But why invest…
Zephyr RTOS + RISC-V – see the live demo at Open Source Summit/Embedded Linux Conference! | Jonathan Beri, GoliothAn Instruction Set Architecture (ISA) is like the DNA of a computer. It’s what makes Arm®-based processors Arm, x86-based CPUs Intel®, and so on. RISC-V…
New release of SweRVolf RISC-V SoC project aims for lower barrier to entry | Gareth Halfacree, The RegisterThe SweRVolf project, a fully open system-on-chip designed as a reference platform for Western Digital's RISC-V SweRV cores, has announced a major new release promising…
Optimization Driving Changes In Microarchitectures | Ann Steffora Mutschler, Semiconductor EngineeringThe semiconductor ecosystem is at a turning point for how to best architect the CPU based on the explosion of data, the increased usage of…
RISC-V Chiplets, Disaggregated Die, and Tiles | Chris Jones, SiFiveScalable High-Performance Computing SoC Design with RISC-V Whether you refer to the design concept as a disaggregated die, tiles, chiplets, or good ol’ multi-chip modules,…
ZAYA now supports RISC-V | ZayaZAYA is a secure operating system that creates a TEE (Trusted Execution Environment) to manage all sensitive operations and resources securely. ZAYA supports and follows…
Open source SystemVerilog tools in ASIC design | Antmicro, Google Open Source BlogOpen source hardware is undeniably undergoing a renaissance whose origin can be traced to the establishment of RISC-V Foundation (later redubbed RISC-V International). The open…
Unlock the RISC-V Naming Code | Richard A. Quinnell, Digi-KeyThe RISC-V instruction set architecture (ISA) provides a unique opportunity. Its structure allows developers to use processors with a wide range of sizes and performance…