No recent posts listed
RISC-V for cars: Infineon announces microcontroller with new computing cores
How The Ubuntu Linux Performance Has Evolved For SiFive RISC-V Over The Last Four Years
CAST Provides a Functional Safety RISC-V Processor IP for the Microchip FPGA’s
Building on a Legacy of Security: Introducing Polar-VPX
Semidynamics launches RISC-V SDK, adds ONNX Runtime support
Soft Tiling RISC-V Processor Clusters Speed Design and Reduce Risk
Baya Systems and Semidynamics Collaborate to Accelerate RISC-V System-on-Chip Development
Breker RISC-V SystemVIP deployed across 15 commercial RISC-V projects
Andes Technology and proteanTecs Partner to Bring Performance and Reliability Monitoring to RISC-V Cores
What’s on tap from RISC-V in 2025?
Memory Safety Will Be Key to Tackle Fundamental Cyber Security
How NVIDIA Shipped One Billion RISC-V Cores In 2024
The Incredible Growth of RISC-V in India
Open Source and CI-driven RTL Testing and Verification for Caliptra’s RISC-V VeeR Core
RISC-V Summit Europe 2023: Highlights from Barcelona
The Call for Papers for RISC-V Summit China 2023 is Open
GreenRio: A Linux-Compatible RISC-V Processor Designed for Open-Source EDA Implementations
Addition of Single Precision Floating Point (F) extension in NucleusRV: RISC-V based RV32-IMC Core
When tapas meet tech: Barcelona’s RISC-V Summit feeds our appetite for innovation
Integrating Tile Link UH in the Caravan Framework: A Journey of Enhanced Functionality
Safety Critical Real-Time Operating System, SAFERTOS® Available With MiV_RV32 Soft CPU
SOPHGO Donates 50 RISC-V Motherboards – Learn More About the Pioneer Box
NOEL-V Processor’s Security Extensions for Safe and Secure Computing
NOEL-V: A RISC-V Processor for High-Performance Space Applications
The Incredible Growth of RISC-V in IndiaOpen Source and CI-driven RTL Testing and Verification for Caliptra’s RISC-V VeeR CoreRISC-V Summit Europe 2023: Highlights from BarcelonaThe Call for Papers for RISC-V Summit China 2023 is OpenGreenRio: A Linux-Compatible RISC-V Processor Designed for Open-Source EDA ImplementationsAddition of Single Precision Floating Point (F) extension in NucleusRV: RISC-V based RV32-IMC CoreWhen tapas meet tech: Barcelona’s RISC-V Summit feeds our appetite for innovationIntegrating Tile Link UH in the Caravan Framework: A Journey of Enhanced FunctionalitySafety Critical Real-Time Operating System, SAFERTOS® Available With MiV_RV32 Soft CPUSOPHGO Donates 50 RISC-V Motherboards – Learn More About the Pioneer BoxNOEL-V Processor’s Security Extensions for Safe and Secure ComputingNOEL-V: A RISC-V Processor for High-Performance Space Applications
[VIDEO] Why the ESP32 C6 DevKit is Perfect for RISC-V Learning
Accelerating SoC Development: A Collaborative Approach by Tenstorrent and Ashling
Gaisler to build 7nm RISC-V chip for space
[VIDEO] Explore the RISC-V in action and how it’s shaping the future of computing.Building your own Yocto image for Banana Pi F3
Jmem Tek unveils first quantum-secure RISC-V chipBritish startup launches low-power RISC-V processor design to address the twin problems of memory and energy; promises up to 50% faster calculation speedsTenstorrent powers first automotive RISC-V AI accelerator chiplet
Semidynamics RISC-V AI IP selected for LLM applications
SiFive Empowers AI at Scale with RISC-V Innovation
TWAIN Working Group joins RISC-V International community to develop secure IoT document scanning solutionsSiFive HiFive Premier P550 RISC-V Price Lowered, Ubuntu 24.04 Support Ready
RISC-V for cars: Infineon announces microcontroller with new computing coresInfineon is increasingly focusing on the open processor instruction set architecture RISC-V. Over the next few years, the manufacturer intends to launch a complete microcontroller…
How The Ubuntu Linux Performance Has Evolved For SiFive RISC-V Over The Last Four YearsSiFive recently sent over their new HiFive Premier P550 developer board and as part of that fresh RISC-V CPU testing I've also been re-testing the…
CAST Provides a Functional Safety RISC-V Processor IP for the Microchip FPGA’sBuild safety-critical automotive, aeronautic, space, and other systems with the Functional Safety RISC-V Processor IP core from CAST and PolarFire FPGAs. By Evan Price, Sales…
Building on a Legacy of Security: Introducing Polar-VPXSundanceDSP, a leading provider of high-performance FPGA-based solutions, is proud to announce the latest addition to its product lineup: Polar-VPX. This cutting-edge 3U VPX form-factor…
Semidynamics launches RISC-V SDK, adds ONNX Runtime supportSemidynamics in Spain has integrated support for its RISC-V AI accelerator hardware IP into the ONNX Runtime environment with the launch of a software development…
Soft Tiling RISC-V Processor Clusters Speed Design and Reduce RiskBy John Min John Min is VP of Customer Success at Arteris. He possesses architectural expertise that enables the successful management of design trade-offs…
Baya Systems and Semidynamics Collaborate to Accelerate RISC-V System-on-Chip DevelopmentSANTA CLARA, Calif. and BARCELONA, Spain, Feb. 25, 2025 /PRNewswire/ -- Baya Systems, a leader in system IP technology that empowers the acceleration of intelligent compute, and Semidynamics, a provider of…
Breker RISC-V SystemVIP deployed across 15 commercial RISC-V projectsBreker Verification Systems confirmed its RISC-V SystemVIP library components and test suite synthesis product portfolio is deployed in more than 15 commercial RISC-V semiconductor design…
Andes Technology and proteanTecs Partner to Bring Performance and Reliability Monitoring to RISC-V CoresTAIPEI, Taiwan & HAIFA, Israel--(BUSINESS WIRE)--Andes Technology Corporation (TWSE: 6533), a leading supplier of RISC-V processor IP, and proteanTecs, a global leader of health and…
What’s on tap from RISC-V in 2025?Andrea Gallo from RVI speaks to JPR’s David Harold about RISC-V’s future. RISC-V is moving towards further standardization with the RVA23 Profile, ensuring software compatibility…
Memory Safety Will Be Key to Tackle Fundamental Cyber SecurityEarlier this month, a U.K. government initiative called Digital Security by Design (DSbD) held a showcase in London to enable companies with pioneering technologies to…
How NVIDIA Shipped One Billion RISC-V Cores In 2024At the recent RISC-V North America summit, NVIDIA’s Vice President of Multimedia Architecture, Frans Sijstermans gave his insight into why NVIDIA chose RISC-V as the…
No recent posts listed
The Incredible Growth of RISC-V in IndiaRISC-V is being adopted around the world as the silicon industry looks to the open RISC-V instruction set architecture (ISA) to offer a new level…
Open Source and CI-driven RTL Testing and Verification for Caliptra’s RISC-V VeeR CoreAs part of CHIPS Alliance’s mission to enable a software-driven approach to silicon, working with Google and other CHIPS members, Antmicro has been developing and improving…
RISC-V Summit Europe 2023: Highlights from BarcelonaMore than 500 attendees, from across the world, attended the first-ever RISC-V Summit Europe Last month, the first-ever RISC-V Summit Europe happened in Barcelona, Spain.…
The Call for Papers for RISC-V Summit China 2023 is OpenRISC-V Summit China is a major international event to share technical and business innovation around RISC-V. The global event brings together the community for a…
GreenRio: A Linux-Compatible RISC-V Processor Designed for Open-Source EDA ImplementationsSince 20 years ago, Intel has successfully developed the 3 GHz processor in 130nm process. However, as the design complexity of IC continues to increase,…
Addition of Single Precision Floating Point (F) extension in NucleusRV: RISC-V based RV32-IMC CoreLinux Foundation Mentorship Spring 2023 at Micro Electronics Research Lab (MERL) sponsored by RISC-V International Abstract The goal of the project is to improve the…
When tapas meet tech: Barcelona’s RISC-V Summit feeds our appetite for innovationBy Brett Cline, Codasip Alright, let's talk about Barcelona. Now, you might be thinking of mouthwatering tapas, smooth local wines, and the pulsing life in…
Integrating Tile Link UH in the Caravan Framework: A Journey of Enhanced FunctionalityWe are thrilled to share the details of our recent project, where we successfully integrated Tile Link UH (Ultra High) into the Caravan framework. Tile…
Safety Critical Real-Time Operating System, SAFERTOS® Available With MiV_RV32 Soft CPUSAFERTOS® is a real-time operating system (RTOS) designed specifically for use in safety-critical systems. WITTENSTEIN high integrity systems is a Mi-V Ecosystem Partner of Microchip…
SOPHGO Donates 50 RISC-V Motherboards – Learn More About the Pioneer BoxNew RISC-V International member SOPHGO is committed to the development and promotion of AI RISC-V CPU and other computing products. RISC-V member Milk-V delivers high-quality…
NOEL-V Processor’s Security Extensions for Safe and Secure ComputingSafety and security are increasingly important aspects when designing computer systems, and work is carried out within RISC-V International technical groups to establish specifications that…
NOEL-V: A RISC-V Processor for High-Performance Space ApplicationsSpace applications pose significant challenges for electronic systems as they must contend with a myriad of environmental factors once they are launched. These factors include…
No recent posts listed
The Incredible Growth of RISC-V in IndiaRISC-V is being adopted around the world as the silicon industry looks to the open RISC-V instruction set architecture (ISA) to offer a new level…
Open Source and CI-driven RTL Testing and Verification for Caliptra’s RISC-V VeeR CoreAs part of CHIPS Alliance’s mission to enable a software-driven approach to silicon, working with Google and other CHIPS members, Antmicro has been developing and improving…
RISC-V Summit Europe 2023: Highlights from BarcelonaMore than 500 attendees, from across the world, attended the first-ever RISC-V Summit Europe Last month, the first-ever RISC-V Summit Europe happened in Barcelona, Spain.…
The Call for Papers for RISC-V Summit China 2023 is OpenRISC-V Summit China is a major international event to share technical and business innovation around RISC-V. The global event brings together the community for a…
GreenRio: A Linux-Compatible RISC-V Processor Designed for Open-Source EDA ImplementationsSince 20 years ago, Intel has successfully developed the 3 GHz processor in 130nm process. However, as the design complexity of IC continues to increase,…
Addition of Single Precision Floating Point (F) extension in NucleusRV: RISC-V based RV32-IMC CoreLinux Foundation Mentorship Spring 2023 at Micro Electronics Research Lab (MERL) sponsored by RISC-V International Abstract The goal of the project is to improve the…
When tapas meet tech: Barcelona’s RISC-V Summit feeds our appetite for innovationBy Brett Cline, Codasip Alright, let's talk about Barcelona. Now, you might be thinking of mouthwatering tapas, smooth local wines, and the pulsing life in…
Integrating Tile Link UH in the Caravan Framework: A Journey of Enhanced FunctionalityWe are thrilled to share the details of our recent project, where we successfully integrated Tile Link UH (Ultra High) into the Caravan framework. Tile…
Safety Critical Real-Time Operating System, SAFERTOS® Available With MiV_RV32 Soft CPUSAFERTOS® is a real-time operating system (RTOS) designed specifically for use in safety-critical systems. WITTENSTEIN high integrity systems is a Mi-V Ecosystem Partner of Microchip…
SOPHGO Donates 50 RISC-V Motherboards – Learn More About the Pioneer BoxNew RISC-V International member SOPHGO is committed to the development and promotion of AI RISC-V CPU and other computing products. RISC-V member Milk-V delivers high-quality…
NOEL-V Processor’s Security Extensions for Safe and Secure ComputingSafety and security are increasingly important aspects when designing computer systems, and work is carried out within RISC-V International technical groups to establish specifications that…
NOEL-V: A RISC-V Processor for High-Performance Space ApplicationsSpace applications pose significant challenges for electronic systems as they must contend with a myriad of environmental factors once they are launched. These factors include…
[VIDEO] Why the ESP32 C6 DevKit is Perfect for RISC-V LearningIn this episode of Product of the Week, Robin Mitchell introduces the ESP32 C6 Dev Kit, a powerful single-board microcontroller platform featuring the latest ESP32…
Accelerating SoC Development: A Collaborative Approach by Tenstorrent and AshlingDecember 4th, 2024 – Silicon Valley, CA – Tenstorrent and Ashling announce a major advancement in SoC development, targeting software bring up and removing debug…
Gaisler to build 7nm RISC-V chip for spaceFrontgrade Gaisler in Sweden has signed a deal with the European Space Agency (ESA) to build a 7nm rad hard chip for space systems using…
[VIDEO] Explore the RISC-V in action and how it’s shaping the future of computing.🚀 Discover how RISC-V is transforming technology across devices. With its open-source, customizable architecture, RISC-V boosts efficiency and enhances performance. 📱💻For smartphones, it delivers faster…
Building your own Yocto image for Banana Pi F3Yocto is the de facto standard for running Linux on embedded systems, and this is of course true for RISC-V as well. We are happy…
Jmem Tek unveils first quantum-secure RISC-V chipJmem Tek has also joined the AndeSentry security collaborative framework, which offers a range of security solutions for Andes RISC-V processors, designed to counter threats…
British startup launches low-power RISC-V processor design to address the twin problems of memory and energy; promises up to 50% faster calculation speedsBlueshift Memory has introduced a new RISC-V processor reference design intended to tackle twin computing challenges: the Memory Wall, caused by slower memory access compared…
Tenstorrent powers first automotive RISC-V AI accelerator chipletBOS Semiconductors in Korea has developed the industry’s first RISC-V AI accelerator chiplet using IP from US startup Tenstorrent. The Eagle-N chiplet was jointly developed by the…
Semidynamics RISC-V AI IP selected for LLM applicationsA leading IP company for high performance, AI-enabled, RISC-V processors, Semidynamics has announced that it has been selected by UPMEM as its core provider for…
SiFive Empowers AI at Scale with RISC-V InnovationArtificial intelligence is increasingly transforming industries, and adopting RISC-V as a flexible and scalable architecture plays a significant role in this shift. Ian Ferguson, senior…
TWAIN Working Group joins RISC-V International community to develop secure IoT document scanning solutionsTWAIN's expanded charter to drive innovation of embedded technologies for IoT devices including 10 billion RISC-V cores that have been shipped into the market RALEIGH,…
SiFive HiFive Premier P550 RISC-V Price Lowered, Ubuntu 24.04 Support ReadyGoing back to April 2024, SiFive announced the HiFive Premier P550 as an interesting RISC-V developer board to succeed their HiFive Unleashed that was a nice little RISC-V board.…