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RISC-V RV32I JALR Instruction | Maven Silicon
Adafruit’s QT Py ESP32-C3, Its First RISC-V Dev Board, Begins Rolling Off the Production Line | Gareth Halfacree, Hackster.io
CEO Interview: Frankwell Lin, Chairman and CEO of Andes Technology | Daniel Nenni, SemiWiki
RISC-V AI Chips Are Joining GPU Race for AI Processing | Paul Mah, CDO Trends
Alphawave IP Announces Definitive Agreement to Acquire Entire OpenFive Business Unit from SiFive for US$210m in cash | Design and Reuse
IAR extends powerful RISC-V solutions with 64-bit support | IAR Systems
Intel Foundry Services Going Big On RISC-V ‘Brawny Cores’ With Ventana Micro Systems Compute Tiles | Patrick Moorhead, Forbes
Exploring emerging trends and topics in RISC-V architecture | Mouser Electronics, ElectroPages
Imperas unifies new RISC-V verification ecosystem with RVVI | Imperas
Mouser Electronics Launches 2022 Empowering Innovation Together Program with New Podcast on RISC-V | Raymond Yin, Business Wire
SEGGER collaboration makes Embedded Studio for RISC-V available at no cost | Neil Tyler, New Electronics
Codasip University Program spurs innovation and boosts curriculums | Codasip
Public Review Period Opens for Proposed RISC-V Scalar Cryptography Extensions | Gareth Halfacree , AB Open
RT-Thread Partnered with WCH Mircoelectronics, to Promote More Applications for RISC-V Ecosystem! | RT-Thread
Video: NixOS/Nix – Cross Compilation via pkgsCross | Matthew Croughan
A Low-Power Asynchronous RISC-V Processor With Propagated Timing Constraints Method | Zhiyu Li, Yuhao Huang, Longfeng Tian, Ruimin Zhu, Shanlin Xiao, and Zhiyi Yu, IEEE XPlore
RISC-V Chiplet Startup Raises $38m, Targets Data Center Compute | Nitin Dahad, EE TimesRNN-Based Radio Resource Management on Multicore RISC-V Accelerator Architectures | Gianna Paulin, Renzo Andri, Francesco Conti, and Luca Benini, IEEE Xplore
Semiconductor veterans gather to design customizable, chiplet-based RISC-V server processors | Chris Williams, The RegisterEnd-to-end 100-TOPS/W Inference With Analog In-Memory Computing: Are We There Yet? | Gianmarco Ottavi, Geethan Karunaratne, Francesco Conti, Irem Boybat, Luca Benini, and Davide Rossi
Andes Technology and Cyberon Collaborate to Provide Edge-Computing Voice Recognition Solution on DSP-capable RISC-V Processors | IntradoSimpira Gets Simpler: Optimized Simpira on Microcontrollers | Minjoo Sim and Siwoo Eum and Hyeokdong Kwon and Kyungbae Jang and Hyunjun Kim and Hyunji Kim and Gyeongju Song and Wai-Kong Lee and Hwajeong Seo, Cryptology ePrint
Video: Apple’s GPU Maker is Designing RISC-V CPUs for Mobiles and Desktops | Gary ExplainsA Novel Compaction Approach for SBST Test Programs | Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, and Matteo Sonza Reorda
RISC-V RV32I JALR Instruction | Maven SiliconThis video explains the RV32I JALR instruction. RISC-V is growing rapidly, follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats,…
Adafruit’s QT Py ESP32-C3, Its First RISC-V Dev Board, Begins Rolling Off the Production Line | Gareth Halfacree, Hackster.ioAdafruit has confirmed that its QT Py ESP32-C3, the company's first development board built around the free and open source RISC-V instruction set architecture, is…
CEO Interview: Frankwell Lin, Chairman and CEO of Andes Technology | Daniel Nenni, SemiWikiFrankwell Lin, Chairman of Andes Technology, started his career being as application engineer in United Microelectronics Corporation (UMC) while UMC was an IDM with its own…
RISC-V AI Chips Are Joining GPU Race for AI Processing | Paul Mah, CDO TrendsA free and open-source instruction set architecture (ISA) is quietly gaining momentum and could well power a significant number of the estimated 25 billion AI…
Alphawave IP Announces Definitive Agreement to Acquire Entire OpenFive Business Unit from SiFive for US$210m in cash | Design and ReuseTransaction will accelerate Alphawave’s connectivity leadership, product offerings and customer base while driving higher scale and revenue growth from an expanded total addressable market. Alphawave…
IAR extends powerful RISC-V solutions with 64-bit support | IAR SystemsIAR Systems extends powerful RISC-V solutions with 64-bit support. Bringing high-performance, well-established technology to companies choosing the emerging RISC-V 64-bit cores for their upcoming development…
Intel Foundry Services Going Big On RISC-V ‘Brawny Cores’ With Ventana Micro Systems Compute Tiles | Patrick Moorhead, ForbesIntel has made a considerable amount of strategic announcements in the past month, whether it be its Tower Semi acquisition, its $20B Ohio investment or…
Exploring emerging trends and topics in RISC-V architecture | Mouser Electronics, ElectroPagesMouser has launched the 2022 series of its Empowering Innovation Together program. This year's series comprises six instalments that spotlight a leading-edge technology that is…
Imperas unifies new RISC-V verification ecosystem with RVVI | ImperasNew open standard RISC-V Verification Interface (RVVI) offers adaptability and verification IP reuse for the expanding community of developers undertaking processor verification. Imperas Software Ltd., the…
Mouser Electronics Launches 2022 Empowering Innovation Together Program with New Podcast on RISC-V | Raymond Yin, Business WireThe first installment of Mouser's 2022 Empowering Innovation Together program zeroes in on RISC-V, including a new episode of The Tech Between Us podcast. Mouser…
SEGGER collaboration makes Embedded Studio for RISC-V available at no cost | Neil Tyler, New ElectronicsThe partnership is focusing on making SEGGER’s multi-platform IDE Embedded Studio available, free of charge, to all HPMicro’s customers using HPM6000 series RISC-V microcontrollers, boosting…
Codasip University Program spurs innovation and boosts curriculums | CodasipKeith Graham appointed Head of University Program. Codasip, the leader in processor design automation, has launched a University Program to help the next generation of…
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Public Review Period Opens for Proposed RISC-V Scalar Cryptography Extensions | Gareth Halfacree , AB OpenThe RISC-V Cryptography Extensions Task Group has opened a public review period on a raft of instruction set extensions, ahead of their planned adoption as…
RT-Thread Partnered with WCH Mircoelectronics, to Promote More Applications for RISC-V Ecosystem! | RT-ThreadRT-Thread has entered into a partnership with WCH Microelectronics to promote more applications in the RISC-V ecosystem. WCH is known in the chip industry for…
Video: NixOS/Nix – Cross Compilation via pkgsCross | Matthew CroughanWatch Matthew Croughan give an introduction to using the Nix CLI to cross-compile packages for other architectures. If you are struggling to enable Flakes, you…
A Low-Power Asynchronous RISC-V Processor With Propagated Timing Constraints Method | Zhiyu Li, Yuhao Huang, Longfeng Tian, Ruimin Zhu, Shanlin Xiao, and Zhiyi Yu, IEEE XPloreOver the past decade, the design of low-power processors is a primary requirement of emerging applications, as Internet of Things (IoT) and neuromorphic chips. Therefore,…
RISC-V Chiplet Startup Raises $38m, Targets Data Center Compute | Nitin Dahad, EE TimesVentana Micro Systems, a RISC-V startup headquartered in Cupertino, CA, has emerged from stealth announcing $38 million in funding and revealing details of its multi-core…
RNN-Based Radio Resource Management on Multicore RISC-V Accelerator Architectures | Gianna Paulin, Renzo Andri, Francesco Conti, and Luca Benini, IEEE XploreRadio resource management (RRM) is critical in 5G mobile communications due to its ubiquity on every radio device and its low latency constraints. The rapidly…
Semiconductor veterans gather to design customizable, chiplet-based RISC-V server processors | Chris Williams, The RegisterA Silicon Valley startup is stepping out of stealth mode today, publicly vowing to supply high-performance data-center-class RISC-V processors. Ventana Micro Systems said since its…
End-to-end 100-TOPS/W Inference With Analog In-Memory Computing: Are We There Yet? | Gianmarco Ottavi, Geethan Karunaratne, Francesco Conti, Irem Boybat, Luca Benini, and Davide RossiIn-Memory Acceleration (IMA) promises major efficiency improvements in deep neural network (DNN) inference, but challenges remain in the integration of IMA within a digital system.…
Andes Technology and Cyberon Collaborate to Provide Edge-Computing Voice Recognition Solution on DSP-capable RISC-V Processors | IntradoCyberon Corporation, a leading embedded speech solution provider, and Andes Technology (TWSE: 6533), a major supplier for high efficiency, low-power 32/64-bit RISC-V processor cores, announced…
Simpira Gets Simpler: Optimized Simpira on Microcontrollers | Minjoo Sim and Siwoo Eum and Hyeokdong Kwon and Kyungbae Jang and Hyunjun Kim and Hyunji Kim and Gyeongju Song and Wai-Kong Lee and Hwajeong Seo, Cryptology ePrintAbstract: Simpira Permutation is a Permutation design using the AES algorithm. The AES algorithm is the most widely used in the world, and Intel has…
Video: Apple’s GPU Maker is Designing RISC-V CPUs for Mobiles and Desktops | Gary ExplainsWatch the full video on Gary Explains. Description: Imagination is returning to the CPU market, this time using RISC-V. It aims to sell designs for…
A Novel Compaction Approach for SBST Test Programs | Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, and Matteo Sonza ReordaIn-field test of processor-based devices is a must when considering safety-critical systems (e.g., in robotics, aerospace, and automotive applications). During in-field testing, different solutions can…