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Rust Cross-Compilation | Daniel Mangum, RISC-V BYTES
Do You Know For Sure Your RISC-V RTL Doesn’t Contain Any Surprises? | Joseph Hupcey III, Semiconductor Engineering
RISC-V CPU Design Courses | Redwood EDA, LLC
Intel May Enable Discrete GPU Driver Development for Arm, RISC-V | Anton Shilov, Tom’s Hardware
Gateway Implementations with RISC-V | Alex Pluemer, Mouser ElectronicsBringing chips back from the dead : MPW-1 Show-off | Sylvain Munaut
Semico Research’s New Report Predicts There Will Be 25 Billion RISC-V-Based AI SoCs By 2027 | Rich Wawrzyniak, Semico Research Corporation
Helping to lead the RISC-V revolution | Solid Sands, Electropages
HIPEAC Info Magazine, January 2022 | HIPEAC
Introduction to FPGA Part 12 – RISC-V Custom Peripheral | Shawn Hymel, Digi-Key Electronics
Open source keystroke injector implementation on the Fomu FPGA board | AntmicroOpen source FPGA platform for Rowhammer security testing in the data center | Antmicro
Bluetrum’s AB32VG1 is Arduino Uno-like RISC-V Based Development Board | Open Cloudware
Thales, IIIT-Delhi Sign MoU On Open Source Hardware R&D | Editorial Team, Open Source for YouZephyr FPGA controller | Antmicro
Picocom Accelerates 5G Communications SoC Development with Cadence Palladium Emulation | 01net, Business Wire
Espressif Expands their RISC-V Portfolio with new ESP32-H2 Thread+Zigbee+BLE SoC | Vishnu Mohanan, Circuit State
Ultra-Low-Power RISC-V System-on-Chip features Adaptive Body Biasing Technology | Abhishek Jadhav, CNX Software
EdgeQ Samples 5G Basestation-on-a-Chip | Sally Ward-Foxton, EE TimesA lightweight ISE for ChaCha on RISC-V | Ben Marshall, Daniel Page, and Thinh Hung Pham, Cryptology
DIY LED Cube For The Masses | Inderpreet Singh, HackadayRISC-V – A Baremetal Introduction using C++ | Phil Mulholland
EdgeQ samples SoC for 5G and AI inference engines | Michael Vizard, Venture BeatA First Look at RISC-V Virtualization from an Embedded Systems Perspective | Bruno Sá, José Martins, and Sandro Pinto
Rust Cross-Compilation | Daniel Mangum, RISC-V BYTESThis is part of a series on the blog where we explore RISC-V by breaking down real programs and explaining how they work. You can view all…
Do You Know For Sure Your RISC-V RTL Doesn’t Contain Any Surprises? | Joseph Hupcey III, Semiconductor EngineeringGiven the relative novelty and complexity of RISC-V RTL designs, whether you are buying a commercially supported core or downloading a popular open-source offering, there…
RISC-V CPU Design Courses | Redwood EDA, LLCThese courses all are made available by Redwood EDA, LLC FREE through June 2022, so enjoy! Computer Architecture is traditionally learned in a university setting…
Intel May Enable Discrete GPU Driver Development for Arm, RISC-V | Anton Shilov, Tom’s HardwareIntel takes aim at Linux enthusiasts with a new initiative. Intel has released request for comments (RFC) patches for its Linux kernel graphics driver enabling…
Gateway Implementations with RISC-V | Alex Pluemer, Mouser ElectronicsReduced instruction-set architectures (ISAs) such as RISC-V provide greater efficiency and less drag on resources than their more complex counterparts. Industrial Internet of Things (IIoT)…
Bringing chips back from the dead : MPW-1 Show-off | Sylvain MunautIn this video I show off the current state of my efforts to bring up the PyFive test chips produced as part of the very…
Semico Research’s New Report Predicts There Will Be 25 Billion RISC-V-Based AI SoCs By 2027 | Rich Wawrzyniak, Semico Research CorporationResearch underscores current RISC-V architecture momentum, emphasizing impressive growth in consumer, enterprise and communication markets RISC-V is leading the open era of computing across…
Helping to lead the RISC-V revolution | Solid Sands, ElectropagesSiFive is creating a new infrastructure to support accelerated ASIC and FPGA design flows, IP delivery, and SoC development. These new developments comprise state-of-the-art compiler…
HIPEAC Info Magazine, January 2022 | HIPEACRead the full edition including RISC-V community member features.
Introduction to FPGA Part 12 – RISC-V Custom Peripheral | Shawn Hymel, Digi-Key ElectronicsA field-programmable gate array (FPGA) is an integrated circuit (IC) that lets you implement custom digital circuits. You can use an FPGA to create optimized…
Open source keystroke injector implementation on the Fomu FPGA board | AntmicroAt Antmicro we work with a large variety of FPGA chips, starting from very large FPGAs we’re using for prototyping ASIC systems, to super small, resource…
Open source FPGA platform for Rowhammer security testing in the data center | AntmicroOur work together with Google and the world’s research community on detecting and mitigating the Rowhammer problem in DRAM memories has been proving that the…
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Bluetrum’s AB32VG1 is Arduino Uno-like RISC-V Based Development Board | Open CloudwareBluetrum, a company known for its high-performance Bluetooth speakers and headsets, had announced to work on open source and popular RISC-V core. So, this Chinese…
Thales, IIIT-Delhi Sign MoU On Open Source Hardware R&D | Editorial Team, Open Source for YouThales and IIIT-Delhi recently signed an agreement for collaborative research and development in the field of Open Hardware and other allied subjects. The collaboration will…
Zephyr FPGA controller | AntmicroThe Zephyr RTOS has seen tremendous growth recently, with almost 1000 contributors and hundreds of platforms supported. Its vendor-neutral, all-encompassing nature has let it spill…
Picocom Accelerates 5G Communications SoC Development with Cadence Palladium Emulation | 01net, Business WireCadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Picocom has deployed the Cadence® Palladium® Enterprise Emulation Platform to accelerate the verification and pre-silicon software…
Espressif Expands their RISC-V Portfolio with new ESP32-H2 Thread+Zigbee+BLE SoC | Vishnu Mohanan, Circuit StateSemiconductor company Espressif Systems expands their RISC-V product portfolio with the addition of a new SoC to their ESP32 family. The new offering is the ESP32-H2, an IEEE 802.15.4 and Bluetooth Low…
Ultra-Low-Power RISC-V System-on-Chip features Adaptive Body Biasing Technology | Abhishek Jadhav, CNX SoftwareCSEM and USJC together have developed an ultra-low-power RISC-V chip for electronic gadgets such as wearables. The semiconductor companies, from Switzerland and Japan respectively, have…
EdgeQ Samples 5G Basestation-on-a-Chip | Sally Ward-Foxton, EE TimesEdgeQ, the startup making basestation-on-a-chip silicon and software for 5G deployments, is now sampling its chip and phy software. The company has also released a…
A lightweight ISE for ChaCha on RISC-V | Ben Marshall, Daniel Page, and Thinh Hung Pham, CryptologyChaCha is a high-throughput stream cipher designed with the aim of ensuring high-security margins while achieving high performance on software platforms. RISC-V, an emerging, free,…
DIY LED Cube For The Masses | Inderpreet Singh, HackadayNo matter what the size or shape of an LED, it brings out the curiosity in every hardware nerd, and is the lifeblood of badge…
RISC-V – A Baremetal Introduction using C++ | Phil MulhollandWhat does it look like to program with no operating system? Can we have direct access to hardware using a high-level language like C++? How…
EdgeQ samples SoC for 5G and AI inference engines | Michael Vizard, Venture BeatEdgeQ revealed today it has begun sampling a 5G base station-on-a-chip that allows AI inference engines to run at the network edge. The goal is…
A First Look at RISC-V Virtualization from an Embedded Systems Perspective | Bruno Sá, José Martins, and Sandro PintoThis article describes the first public implementation and evaluation of the latest version of the RISC-V hypervisor extension (H-extension v0.6.1) specification in a Rocket chip…