No recent posts listed
Board with 25 RGB LEDs is offered with ESP32-C3 or ESP32-Pico-D4 | Jean-Luc Aufranc, CNX Software
New Part Day: The RISC-V Lichee-RV Module and Dock | Dave Rowntree, Hackaday
CFU Playground: Full-Stack Open-Source Framework for Tiny Machine Learning (tinyML) Acceleration on FPGAs | Shvetank Prakash∗, Tim Callahan† Joseph Bushagour§, Colby Banbury∗, Alan V. Green†, Pete Warden†, Tim Ansell†, Vijay Janapa Reddi∗, †Google §Purdue University ∗Harvard UniversitySiFive announced new, high performance RISCV cores as AMD is looking for RISCV architect? | René Rebe, Bits inside by René Rebe
When You Reach The Summit, Keep Climbing | Andy Frame, SiFive
Using Imagination Around Arm & RISC-V | Embedded Computing Design Staff, Embedded Computing Design
RISC-V CTO: We won’t dictate chip design like Arm and x86 | Agam Shah, The Register
Mobileye Announces EyeQ6 And EyeQ Ultra Chips For Assisted And Automated Driving | Sam Abuelsamid, Forbes
Simodense: a RISC-V softcore optimised for exploring custom SIMD instructions | Philippos Papaphilippou, Kelly Paul H. J., and Wayne Luk
Podcast EP54: Ventana Micro, RISC-V, HPC and Chiplets | Daniel Nenni, Semiwiki
Israeli Tech Industry to Get New Processor for Free, Courtesy of the State | Sagi Cohen, Haaretz
SATA Design Implementation on FPGAs with Open Source Tools | CHIPS Alliance
Andes certifies Imperas RISC-V Reference Models for the new RISC-V P (SIMD/DSP) extension
NodeMCU Launches Sub-$5 Espressif ESP32-C3 RISC-V Development Boards | Gareth Halfacree, Hackster.ioRISC-V Bytes: Introduction to Instruction Formats | Daniel MangumBringing OpenCL to Commodity RISC-V CPUs | Tine Blaise, Seyong Lee, Jeff Vetter, and Hyesoon Kim, Georgia Institute of Technology
A Look At The ET-SoC-1, Esperanto’s Massively Multi-Core RISC-V Approach To AI | David Schor, WikiChip Fuse
Huami Will Unveil Self-developed OS, Chip, GPU at Next Beat 2021 Conference | Kamlesh Bhati, Sparrows News
Building occupancy management solution using the TensorFlow Object Detection API | GreenWaves TechnologiesA Survey on RISC-V Security: Hardware and Architecture | Tao Lu, Marvell Semiconductor Ltd
Fraunhofer IPMS RISC-V processor core for functional safety supported by development tools from IAR Systems | Franka Balvin, IDWCanaan Announces Kendryte K510 Edge AI Chip as a Triple-Core RISC-V Part with 3 TOPS NPU | Gareth Halfacree, Hackster.io
Kendryte K510 tri-core RISC-V AI processor deliver up to 3 TOPS | Jean-Luc Aufranc, CNX SoftwareFraunhofer IPMS RISC-V processor core for functional safety supported by development tools from IAR Systems | Design & Reuse
Board with 25 RGB LEDs is offered with ESP32-C3 or ESP32-Pico-D4 | Jean-Luc Aufranc, CNX SoftwareIn case you are in need of a tiny WiFI or Bluetooth-connected board with an RGB LED matrix, two have shown up on Banggood with…
New Part Day: The RISC-V Lichee-RV Module and Dock | Dave Rowntree, HackadaySipeed have been busy leveraging developments in the RISC-V arena, with an interesting, low-cost module they call the Lichee RV. It is based around the Aliwinner D1…
CFU Playground: Full-Stack Open-Source Framework for Tiny Machine Learning (tinyML) Acceleration on FPGAs | Shvetank Prakash∗, Tim Callahan† Joseph Bushagour§, Colby Banbury∗, Alan V. Green†, Pete Warden†, Tim Ansell†, Vijay Janapa Reddi∗, †Google §Purdue University ∗Harvard UniversityAbstract: We present CFU Playground, a full-stack open-source framework that enables rapid and iterative design of machine learning (ML) accelerators for embedded ML systems. Our…
SiFive announced new, high performance RISCV cores as AMD is looking for RISCV architect? | René Rebe, Bits inside by René Rebe#SiFive p650 high performance #RISCV cores w/ Vector and Hypervisor extension while AMD is hiring RISCV engineers, too?! Watch the full video.
When You Reach The Summit, Keep Climbing | Andy Frame, SiFiveThe RISC-V Summit 2021 highlighted to the world that the future of RISC-V has no limits! 2021 has been an outstanding year for SiFive, and…
Using Imagination Around Arm & RISC-V | Embedded Computing Design Staff, Embedded Computing DesignChampions of the open-standard ISA expect it to start displacing competitive offerings en masse over the next few years. While that remains to be seen,…
RISC-V CTO: We won’t dictate chip design like Arm and x86 | Agam Shah, The RegisterChip technologies from Arm and x86 are getting the most attention amid semiconductor shortages and trade wars. But in the background, the open-source RISC-V chip…
Mobileye Announces EyeQ6 And EyeQ Ultra Chips For Assisted And Automated Driving | Sam Abuelsamid, ForbesMobileye and its parent company Intel may not be attending CES 2022 in person, but they are making some news.The Israel-based market leader in vision-based advanced…
Simodense: a RISC-V softcore optimised for exploring custom SIMD instructions | Philippos Papaphilippou, Kelly Paul H. J., and Wayne LukAbstract: Simodense is a high-performance open-source RISC-V (RV32IM) softcore, optimised for exploring custom SIMD instructions. In order to maximise SIMD instruction performance, the design’s memory…
Podcast EP54: Ventana Micro, RISC-V, HPC and Chiplets | Daniel Nenni, SemiwikiDan is joined by Balaji Baktha, founder and CEO of Ventana Micro. Balaji explores the application of RISC-V in high-performance applications and the specific advantages of a chiplet-based…
Israeli Tech Industry to Get New Processor for Free, Courtesy of the State | Sagi Cohen, HaaretzThe Israel Innovation Authority wants to let local high-tech companies use a processor developed in Israel with some state funding for free, thereby enabling them…
SATA Design Implementation on FPGAs with Open Source Tools | CHIPS AllianceReal-world FPGAs designs often require high rate transmission protocols such as PCIe, USB and SATA which rely on high speed transceivers for external communication. These…
No recent posts listed
No recent posts listed
No recent posts listed
No recent posts listed
Andes certifies Imperas RISC-V Reference Models for the new RISC-V P (SIMD/DSP) extensionImperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today announced that Andes Technology Corp., a leading supplier of performance-efficient and extensible 32/64-bit…
NodeMCU Launches Sub-$5 Espressif ESP32-C3 RISC-V Development Boards | Gareth Halfacree, Hackster.ioThe first commercial development boards featuring Espressif's RISC-V-based ESP32-C3, a drop-in replacement for the popular ESP8266, have appeared on the market — costing as little…
RISC-V Bytes: Introduction to Instruction Formats | Daniel MangumThis is part of a series on the blog where we explore RISC-V by breaking down real programs and explaining how they work. You can view all…
Bringing OpenCL to Commodity RISC-V CPUs | Tine Blaise, Seyong Lee, Jeff Vetter, and Hyesoon Kim, Georgia Institute of TechnologyThe importance of open-source hardware has been increasing in recent years with the introduction of the RISC-V Open ISA. This has also accelerated the push…
A Look At The ET-SoC-1, Esperanto’s Massively Multi-Core RISC-V Approach To AI | David Schor, WikiChip FuseAsk ten different engineers how they would design an AI accelerator and you’ll get ten different ways to arrange the billions of transistors on a…
Huami Will Unveil Self-developed OS, Chip, GPU at Next Beat 2021 Conference | Kamlesh Bhati, Sparrows NewsThe well-known smart wearable device manufacturers Huami Technology previously announced that it will hold the Next Beat 2021 conference on July 13, the theme of…
Building occupancy management solution using the TensorFlow Object Detection API | GreenWaves TechnologiesGreenWaves has developed a people counting solution for occupancy management in smart building systems, providing real-time insights into how available space is used by employees…
A Survey on RISC-V Security: Hardware and Architecture | Tao Lu, Marvell Semiconductor LtdThe Internet of Things (IoT) is an ongoing technological revolution. Embedded processors are the processing engines of smart IoT devices. For decades, these processors were…
Fraunhofer IPMS RISC-V processor core for functional safety supported by development tools from IAR Systems | Franka Balvin, IDWWith its latest release of development tools for RISC-V processors, Swedish software manufacturer IAR Systems offers support for the ISO 26262 ASIL-D ready certified RISC-V…
Canaan Announces Kendryte K510 Edge AI Chip as a Triple-Core RISC-V Part with 3 TOPS NPU | Gareth Halfacree, Hackster.ioCanaan has announced the sampling of a RISC-V chip designed specifically for edge AI workloads, at the World Artificial Intelligence Conference 2021: the Kendryte K510.…
Kendryte K510 tri-core RISC-V AI processor deliver up to 3 TOPS | Jean-Luc Aufranc, CNX SoftwareKendryte K510 is a 64-bit tri-core RISC-V processor clocked at up to 800 MHz with AI accelerators that succeed the 400 MHz Kendryte K210 dual-core RISC-V…
Fraunhofer IPMS RISC-V processor core for functional safety supported by development tools from IAR Systems | Design & ReuseWith its latest release of development tools for RISC-V processors, Swedish software manufacturer IAR Systems offers support for the ISO 26262 ASIL-D ready certified RISC-V…