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Inside RISC-V: Analysis and Exploitation | Don A. Bailey via Ringzer0
A Heterogeneous In-Memory Computing Cluster For Flexible End-to-End Inference of Real-World Deep Neural Networks | Angelo Garofalo∗, Gianmarco Ottavi∗, Francesco Conti∗, Geethan Karunaratne†‡, Irem Boybat†, Luca Benini‡∗, Davide Rossi∗, ∗University of Bologna, Bologna, Italy, †IBM Research Europe, Zurich, Switzerland, ‡ETH Zurich, Zurich, Switzerland
Intel Mobileye EyeQ Ultra RISC-V processor targets Level 4 autonomous driving | Jean-Luc Aufranc, CNX Software
This $5 dock turns the $17 Sipeed Lichee RV into a fully functional RISC-V computer | Brad Linder, Liliputing
CEO Interview: Igor Spinella, Eggtronic | Nick Flaherty, EE News Europe
64-bit RISC-V support added to new software release | SEGGER, Electropages
Sharing files between host and simulated platform in Renode with Virtio and other means | AntmicroCH583 RISC-V microcontroller supports Bluetooth 5.3 LE | Jean-Luc Aufranc, CNX SoftwareSipeed Lichee RV RISC-V module gets $5+ carrier board with HDMI and USB ports, optional WiFi | Jean-Luc Aufranc, CNX Software
Edge AI on Low-Footprint RISC-V | Alexander Stanitzki, Fraunhofer IMSLoRaWAN on Apache NuttX OS | Lup Yuen Lee, Mr. Tech Blog
RISC-V Reaches Adolescence | Brian Santo, EE Times
Embedded development board features Microchip PolarFire RISC-V FPGA SoC | Jean-Luc Aufranc, CNX Software
Fraunhofer IPMS RISC-V processor core for functional safety supported by development tools from IAR Systems
Suse Tumbleweed Gets RubyGems Updates, New systemd
SBC builds on PolarFire SoC with dual GbE and CAN | Eric Brown, Linux Gizmos
Video: tinyML Talks France – State of the TinyML todayOpen Source Mindset with Michael Gielda | The Amp Hour
Zephyr RTOS Virtualization and Memory Isolation | Zephyr ProjectVideo: How to make a 32-bit RISC-V CPU
Video: Homemade 32-bit RISC-V CPU | JLCPCB
Chinese chip designers hope to topple Arm’s Cortex-A76 with XiangShan RISC-V design | Gareth Halfacree, The Register
GreenWaves releases Profiler – A visualization tool for profiling and debugging GAP applicationsXiangShan open-source 64-bit RISC-V processor to rival Arm Cortex-A76 | Jean-Luc Aufranc, CNX Software
Inside RISC-V: Analysis and Exploitation | Don A. Bailey via Ringzer0Don's 90 minute introduction to RISC-V gives you a sneak peek into the attack surface of RISC-V architecture CPUs and what it would take to…
A Heterogeneous In-Memory Computing Cluster For Flexible End-to-End Inference of Real-World Deep Neural Networks | Angelo Garofalo∗, Gianmarco Ottavi∗, Francesco Conti∗, Geethan Karunaratne†‡, Irem Boybat†, Luca Benini‡∗, Davide Rossi∗, ∗University of Bologna, Bologna, Italy, †IBM Research Europe, Zurich, Switzerland, ‡ETH Zurich, Zurich, SwitzerlandAbstract—Deployment of modern TinyML tasks on small battery-constrained IoT devices requires high computational energy efficiency. Analog In-Memory Computing (IMC) using non-volatile memory (NVM) promises major…
Intel Mobileye EyeQ Ultra RISC-V processor targets Level 4 autonomous driving | Jean-Luc Aufranc, CNX SoftwareLet’s carry on with Intel’s CES 2022 news, but with a twist as Mobileye EyeQ Ultra does not include any x86 cores, but instead, the automotive…
This $5 dock turns the $17 Sipeed Lichee RV into a fully functional RISC-V computer | Brad Linder, LiliputingThe Sipeed Lichee RV is an inexpensive computer-on-a-module featuring an Allwinner D1 RISC-V processor, 512MB of RAM, and a microSD card reader for storage. First…
CEO Interview: Igor Spinella, Eggtronic | Nick Flaherty, EE News EuropeIgor Spinella talks to Nick Flaherty about raising €15m for a family of RISC-V power controllers that will be used in AC power sockets around…
64-bit RISC-V support added to new software release | SEGGER, ElectropagesSEGGER's latest release of Embedded Studio for RISC-V added support for 64-bit RISC-V CPUs, including RV64I, RV64E and RV64GC with floating-point unit. It is provided…
Sharing files between host and simulated platform in Renode with Virtio and other means | AntmicroRenode is an open-source hardware simulation framework developed by Antmicro. Thanks to its modularity and configurability it can simulate a wide range of platforms and…
CH583 RISC-V microcontroller supports Bluetooth 5.3 LE | Jean-Luc Aufranc, CNX SoftwareFollowing up on the CH572 RISC-V BLE microcontroller with 10KB SRAM, WCH has now introduced the CH583 RISC-V microcontroller with 32KB SRAM, 1 MB flash,…
Sipeed Lichee RV RISC-V module gets $5+ carrier board with HDMI and USB ports, optional WiFi | Jean-Luc Aufranc, CNX SoftwareSipeed introduced the Lichee RV Allwinner D1 Linux RISC-V board going for just $17 with 512MB RAM last month. While with a USB-C port it…
Edge AI on Low-Footprint RISC-V | Alexander Stanitzki, Fraunhofer IMSThe integration of AI algorithms on end devices (“Edge AI”, “AI of Things”, TinyML,..) is conquering the domain of resource constrained microcontrollers and cost-efficient ASIC…
LoRaWAN on Apache NuttX OS | Lup Yuen Lee, Mr. Tech BlogLast article we got LoRa (the long-range, low-bandwidth wireless network) running on Apache NuttX OS… “LoRa SX1262 on Apache NuttX OS” Today we shall run LoRaWAN on NuttX OS! …
RISC-V Reaches Adolescence | Brian Santo, EE TimesThe microprocessor market has been remarkably homogeneous for a very long time. Two camps currently dominate. One surrounds the x86 architecture, the other follows Arm.…
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Embedded development board features Microchip PolarFire RISC-V FPGA SoC | Jean-Luc Aufranc, CNX SoftwareMicrochip/MicroSemi first introduced PolarFire RISC-V FPGA SoC at the end of 2018, with the chip being like the RISC-V equivalent of Xilinx Zynq Ultrascale+ Arm & FPGA…
Fraunhofer IPMS RISC-V processor core for functional safety supported by development tools from IAR SystemsWith its latest release of development tools for RISC-V processors, Swedish software manufacturer IAR Systems offers support for the ISO 26262 ASIL-D ready certified RISC-V…
Suse Tumbleweed Gets RubyGems Updates, New systemdA total of four openSUSE Tumbleweed snapshots have been released since the last update. Three smaller snapshots, which included a new systemd update, and one large snapshot, which included…
SBC builds on PolarFire SoC with dual GbE and CAN | Eric Brown, Linux GizmosAldec announced a “TySOM-M-MPFS250” SBC that runs Linux on Microchip’s RISC-V based, FPGA equipped PolarFire SoC and offers 2x GbE, 2x FMC, 2x micro-USB, PCIe…
Video: tinyML Talks France – State of the TinyML todayThe 1st TinyML meetup was held virtually as an open panel discussion with the keynote speakers. The group discussed the landscape and potential of today’s…
Open Source Mindset with Michael Gielda | The Amp HourThe Amp Hour Podcast welcomes back Antmicro's Michael Gielda who was on episode 519 talking about simulating embedded hardware using Renode He returned to talk…
Zephyr RTOS Virtualization and Memory Isolation | Zephyr ProjectAlmost 700 people registered for the first-ever Zephyr Developer Summit, which took place virtually on June 8-10, to learn more about the RTOS. We had…
Video: How to make a 32-bit RISC-V CPUWatch a video tutorial showing the steps involved in creating a 32-bit RISC-V CPU. See the full video here.
Video: Homemade 32-bit RISC-V CPU | JLCPCBWatch Filip Szkandera talk about a homemade 32-bit RISC-V CPU. It runs at 500 kHz, has 512 kB RAM & program memory. VGA output is…
Chinese chip designers hope to topple Arm’s Cortex-A76 with XiangShan RISC-V design | Gareth Halfacree, The RegisterThe Institute of Computing Technology at the Chinese Academy of Sciences (ICT CAS) has showcased progress on a fully open-source processor, designed around the RISC-V…
GreenWaves releases Profiler – A visualization tool for profiling and debugging GAP applicationsProfiler is a part of our GAP SDK and used with GVSOC, our Full System SoC Simulator. Profiler gives you a visual view of what…
XiangShan open-source 64-bit RISC-V processor to rival Arm Cortex-A76 | Jean-Luc Aufranc, CNX SoftwareSiFive Performance P550 was supposed to be the most powerful RISC-V core to date, capable of outperforming Arm’s Cortex-A75 core in raw performance, but especially in…