No recent posts listed
M5Stamp C3 RISC-V board supports WiFI 4, Bluetooth 5.0 Long Range and 2 Mbps bitrate | Jean-Luc Aufranc, CNX Software
Video: SMK68 – OpenSource RISCV Custom Mechanical Keyboard | Caesar WuAlibaba open sources four RISC-V cores: XuanTie E902, E906, C906 and C910 | Jean-Luc Aufranc, CNX Software
De-RISC, the H2020 project which will create the first RISC-V fully European platform for aerospace, celebrates its second anniversary | Design and Reuse
Linley Fall Processor Conference 2021 | The Linley Group
The Basics of RISC-V: The Free Open Source Instruction Set | The New Stack
Power/Performance Bits: Oct. 19 | Jesse Allen, Semiconductor Engineering
Alibaba Announces Open Source RISC-V-Based Xuantie Series Processors | Pandaily
De-RISC – The H2020 Project Which Will Create The First RISC-V Fully European Platform For Aerospace, Celebrates Its Second Anniversary | Ana Rísquez Navarro, De-RISC
Andes Technology USA Corp. Announces Major Expansion of Its U.S. Operation | Andes Technology
Andes Presents “Datacenter Accelerators Using RISC-V” at Linley Fall Processor Conference 2021 | Chip Estimate
Segger licenses ARM and RISC-V compiler and linker to toolchain providers | Nick Flaherty , EE News Europe
New MPW-TWO Program Will Provide Fabrication For Fully Open Source Projects | Rob Mains, CHIPS Alliance
Antmicro’s ARV RISC-V SoM announced | Ant Micro
Filip Szkandera’s Pineapple ONE Is a RISC-V Computer Built Entirely From Discrete Logic Components | Gareth Halfacree, hackster.io
Embedded Executive: Mark Himelstein, CTO, RISC-V | Rich Nass, Embedded Computing DesignMark
Adding Value To Open-Source RISC-V Cores With Verification | Lee Moore, Semiconductor Engineering
Goings-on in the FuseSoC project and other Open Source Silicon related news | Olof Kindgren
Video: neXt Curve Webcast: RISC V – Ready or Not?New Methodologies Create New Opportunities | Brian Bailey, Semiconductor EngineeringVideo: PULSE Sensor Demo using VEGA Processor [ RISC-V ISA] | VEGA Processors
Video: New Online Courses For RISC-V | Linux Foundation
Pineapple ONE 32 bit RISC-V homemade CPU | filip.szkandera
M5Stamp C3 RISC-V board supports WiFI 4, Bluetooth 5.0 Long Range and 2 Mbps bitrate | Jean-Luc Aufranc, CNX SoftwareIt was only last month that M5Stack launched the M5Stamp Pico module based on an ESP32-PICO-D4 SiP and heat-resistant plastic shell, but M5Stamp C3 board…
Video: SMK68 – OpenSource RISCV Custom Mechanical Keyboard | Caesar WuSMK68:OpenSource RISC-V Custom Mechanical Keyboard with Programmable OLED & Keys, RGB, Hot-swappable, USB/BLE Dual-Mode, even Serial Terminal; SMK68, most Geekery Keyboard for you! Watch the…
Alibaba open sources four RISC-V cores: XuanTie E902, E906, C906 and C910 | Jean-Luc Aufranc, CNX SoftwareAlibaba introduces a range of RISC-V processors in the last few years with the Xuantie family ranging from the E902 micro-controller class core to the…
De-RISC, the H2020 project which will create the first RISC-V fully European platform for aerospace, celebrates its second anniversary | Design and ReuseThe De-RISC Project celebrates its second year through the introduction of a market-ready hardware-software platform based on the RISC-V instruction set architecture (ISA), productizing a…
Linley Fall Processor Conference 2021 | The Linley GroupFor more than a decade, The Linley Group has delivered the industry’s premier processor conferences. This year, the Linley Fall Processor Conference will return to…
The Basics of RISC-V: The Free Open Source Instruction Set | The New StackIn this presentation by Calista Redmond, CEO, & Stephano Cetola, Director of Tech Programs, at Open Source Summit 2021, we explore the basics of RISC-V,…
Power/Performance Bits: Oct. 19 | Jesse Allen, Semiconductor EngineeringResearchers at the Technical University of Munich (TUM) designed and had fabricated an ASIC to run new encryption algorithms that can stand up to quantum…
Alibaba Announces Open Source RISC-V-Based Xuantie Series Processors | PandailyAt the 2021 Apsara Conference on Tuesday, Zhang Jianfeng, President of Alibaba Cloud Intelligence, announced T-Head’s open source RISC-V-based Xuantie series processors and a series…
De-RISC – The H2020 Project Which Will Create The First RISC-V Fully European Platform For Aerospace, Celebrates Its Second Anniversary | Ana Rísquez Navarro, De-RISCThe De-RISC Project celebrates its second year through the introduction of a market-ready hardware-software platform based on the RISC-V instruction set architecture (ISA), productizing a…
Andes Technology USA Corp. Announces Major Expansion of Its U.S. Operation | Andes TechnologySan Jose, Oct. 11, 2021 (GLOBE NEWSWIRE) -- Andes Technology USA Corp., the headquarters of North America operations of Hsinchu, Taiwan-based Andes Technology Corporation, a…
Andes Presents “Datacenter Accelerators Using RISC-V” at Linley Fall Processor Conference 2021 | Chip EstimateWhat: The 2021 Linley Fall Processor Conference analyzes products and design strategies in a particular technology segment, providing information that engineers can immediately use to…
Segger licenses ARM and RISC-V compiler and linker to toolchain providers | Nick Flaherty , EE News EuropeSegger in Germany has made its compiler and linker available for licensing to IDE and toolchain providers. The components can be easily integrated into development…
No recent posts listed
No recent posts listed
No recent posts listed
No recent posts listed
New MPW-TWO Program Will Provide Fabrication For Fully Open Source Projects | Rob Mains, CHIPS AllianceCHIPS Alliance is excited to announce that the hardware development community can submit their open source design projects to Efabless.com for space on their forthcoming…
Antmicro’s ARV RISC-V SoM announced | Ant MicroWe are excited to announce the ARV SoM - Antmicro’s fully open source, RISC-V-based system-on-module featuring the StarFive 71x0 SoC. Using the RISC-V architecture, which…
Filip Szkandera’s Pineapple ONE Is a RISC-V Computer Built Entirely From Discrete Logic Components | Gareth Halfacree, hackster.ioRunning at just 500kHz, this multi-board computer is surprisingly functional — and could form the basis for an open source educational kit. Read the article.
Embedded Executive: Mark Himelstein, CTO, RISC-V | Rich Nass, Embedded Computing DesignMarkThere’s no moss gathering on the RISC-V stone. The group continues to make progress in just about all facets of its roadmap. To understand what…
Adding Value To Open-Source RISC-V Cores With Verification | Lee Moore, Semiconductor EngineeringA collaboration to verify a PULP RI5CY core using industrial grade techniques provides a set of guidelines for the community. By Steve Richmond (Silicon Labs), Mike Thompson…
Goings-on in the FuseSoC project and other Open Source Silicon related news | Olof KindgrenA first look at Edalize for ASIC flows Over the past years there has been a revolution in open source silicon. While there have been…
Video: neXt Curve Webcast: RISC V – Ready or Not?The semiconductor industry has never faced a more tumultuous and exciting time than now. Competition, innovations, and geopolitics are forcing tectonic shifts in the industry…
New Methodologies Create New Opportunities | Brian Bailey, Semiconductor EngineeringDoes RISC-V processor verification provide common ground to develop a new verification methodology, and will that naturally lead to new and potentially open tools? Experts…
Video: PULSE Sensor Demo using VEGA Processor [ RISC-V ISA] | VEGA ProcessorsDemonstrating PULSE Sensor using VEGA Microprocessor based on RISC-V ISA
Video: New Online Courses For RISC-V | Linux FoundationRISC-V is a free and open instruction set architecture (ISA) enabling a new era of processor innovation through open standard collaboration. To help individuals get…
Pineapple ONE 32 bit RISC-V homemade CPU | filip.szkanderaIn this article I will describe how I designed and made a functional 32 bit RISC-V CPU at home. Specifications: "Max" clock speed: 500 kHz…