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RISC-V CEO: The biggest opportunity to change computing since the 1980s | Tiernan Ray, ZDNet
Rolf Segger on the chip shortage | Nick Flaherty , EE News Europe
Secure FPGA RISC-V SoC Forgoes Heatsink | William G. Wong, Electronic Design
SEGGER Releases Floating Point Library to Support RISC-V | Raspberry Pi Projects
Mythic Licenses Codasip’s L30 RISC-V Core for Next-Generation AI Processor |
Announcing public review for RISC-V standard extensions Zfinx, Zdinx, Zhinx, and Zhinxmin
Researchers Develop RISC-V Chip for Quantum-Resistant Encryption | Francisco Pires, Tom’s Hardware
TUM Researchers Design Chip for ‘Post Quantum’ Cryptography | John Russell, HPC Wire
Video: Booting the HiFive Unmatched board | Gábor SamuVideo: Glitching RISC-V chips: MTVEC corruption for hardening ISA | Adam Zabrocki and Alex Matrosov, DEF CON 29
Open source SystemVerilog tools in ASIC designOpen source SystemVerilog tools in ASIC design
Video: OSDI 21 – The nanoPU: A Nanosecond Network Stack for Datacenters
Developing Diosix: An open-source RISC-V bare-metal hypervisor from scratch in Rust | British Computer Society Open Source Specialists
Expanding a RISC-V Processor with Vector Instructions for Accelerating Machine Learning | British Computer Society Open Source Specialists
Micro Magic, Inc. Delivers Ultra Low Power 64-Bit RISC-v Core | Cision PR Newswire
RISC-V Awareness Webinar From Dr. Ali Ahmed and Zeeshan Rafique from UIT | Micro Electronics Research Lab -UIT
CUSTOMIZING AN EXISTING RISC-V PROCESSOR | Codasip
A Look Back At 2020: Another Strong Year Of Growth For Andes Despite The Pandemic | Andes Technology
HANDS-ON: THE RISC-V ESP32-C3 WILL BE YOUR NEW ESP8266 | Elliot Williams, Hackaday
RISC-V: Q&A with SiFive head of global communications James Prior | Judy Lin, DIGITIMES
“Open ISAs (RISC-V, OpenPOWER, etc)” – Alistair Francis, Hugh Blemings (LCA 2021 Online) | linux.conf.au
Securing RISC-V-Based Systems | Max Maxfield, Electronic Engineering Journal
Electronic industry trends for 2021 | Dunstan Power, newelectronics
RISC-V CEO: The biggest opportunity to change computing since the 1980s | Tiernan Ray, ZDNetCalista Redmond, chief executive of the microprocessor consortium RISC-V International, is a fan of the wild days of chip competition back in the 1980s. "This…
Rolf Segger on the chip shortage | Nick Flaherty , EE News EuropeRolf Segger, founder of Segger Microcontroller, talks to Nick Flaherty at eeNews Europe about the chip shortage, RISC-V, China and the need for embedded security…
Secure FPGA RISC-V SoC Forgoes Heatsink | William G. Wong, Electronic DesignVery-low-power FPGAs have been around for a while, but often there’s the need for those that can handle high-speed serial interfaces like PCI Express or…
SEGGER Releases Floating Point Library to Support RISC-V | Raspberry Pi ProjectsSEGGER‘s stand-alone Floating-Point Library has now been extended to include an assembly-optimized variant for RISC-V implementations. The library contains a complete set of high level…
Mythic Licenses Codasip’s L30 RISC-V Core for Next-Generation AI Processor |Codasip, the leading supplier of customizable RISC-V® embedded processor IP, announced today that Mythic, the pioneering AI processor company with breakthrough analog compute-in-memory technology, has…
Announcing public review for RISC-V standard extensions Zfinx, Zdinx, Zhinx, and ZhinxminThe RISC-V Zfinx Task Group is thrilled to announce the Zfinx extension (pronounced “z-f-in-x”) has entered the public review period. The Zfinx extension brings the…
Researchers Develop RISC-V Chip for Quantum-Resistant Encryption | Francisco Pires, Tom’s HardwareA research team with the Technical University of Munich (TUM) have designed a quantum cryptography chip aimed at the security demands of the quantum computing revolution. The…
TUM Researchers Design Chip for ‘Post Quantum’ Cryptography | John Russell, HPC WireResearchers from the Technical University of Munich (TUM) have designed and commissioned fabrication of chip intended to implement so-called post-quantum cryptography. The ASIC’s design is…
Video: Booting the HiFive Unmatched board | Gábor SamuSee Gábor Samu booting Ubuntu 21.04 on the SiFive HiFive Unmatched developer board. This was captured via the onboard serial port. Visit his blog for…
Video: Glitching RISC-V chips: MTVEC corruption for hardening ISA | Adam Zabrocki and Alex Matrosov, DEF CON 29View the full video and description on the DEF CON YouTube Channel. Presentation Summary: RISC-V is an open standard instruction set architecture (ISA) provided under…
Open source SystemVerilog tools in ASIC designOpen source SystemVerilog tools in ASIC designOpen source hardware is undeniably undergoing a renaissance whose origin can be traced to the establishment of RISC-V Foundation (later redubbed RISC-V International). The open…
Video: OSDI 21 – The nanoPU: A Nanosecond Network Stack for DatacentersThe nanoPU: A Nanosecond Network Stack for Datacenters by Stephen Ibanez, Alex Mallery, Serhat Arslan, and Theo Jepsen, Stanford University; Muhammad Shahbaz, Purdue University; Changhoon…
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Developing Diosix: An open-source RISC-V bare-metal hypervisor from scratch in Rust | British Computer Society Open Source SpecialistsDiosix bridges two interesting and emerging worlds of technology: Rust and RISC-V. As a bare-metal, type-1 hypervisor, Diosix strives to bring the security, reliability, and…
Expanding a RISC-V Processor with Vector Instructions for Accelerating Machine Learning | British Computer Society Open Source SpecialistsPresented by Pete Alexander, John Holden, Harry Cooper, Byron Theobald, Aaryaman Bhattacharya, Matthew Johns, University of Southampton The open-source RISC-V instruction set architecture is gaining…
Micro Magic, Inc. Delivers Ultra Low Power 64-Bit RISC-v Core | Cision PR NewswireSUNNYVALE, Calif., Feb. 12, 2021 /PRNewswire/ -- Today, Micro Magic, Inc. announced its Ultra Low power 64-bit RISC-V core consuming only 10mW at 1Ghz. Micro Magic's design techniques allow…
RISC-V Awareness Webinar From Dr. Ali Ahmed and Zeeshan Rafique from UIT | Micro Electronics Research Lab -UITThis webinar was arranged to bring awareness and to tell the importance of RISC-V to Pakistani students. This presentation includes: RISC-V introduction RISC-V achievements globally…
CUSTOMIZING AN EXISTING RISC-V PROCESSOR | CodasipIn the previous post, we considered how you could create an optimized ISA for a domain-specific processor core by profiling software and experimenting with adding/removing instructions.…
A Look Back At 2020: Another Strong Year Of Growth For Andes Despite The Pandemic | Andes TechnologyIn 2020, although the COVID-19 pandemic had a severe impact on the global economy, Andes Technology still made significant advances and achievements in the development…
HANDS-ON: THE RISC-V ESP32-C3 WILL BE YOUR NEW ESP8266 | Elliot Williams, HackadayWe just got our hands on some engineering pre-samples of the ESP32-C3 chip and modules, and there’s a lot to like about this chip. The question…
RISC-V: Q&A with SiFive head of global communications James Prior | Judy Lin, DIGITIMESRISC-V has grabbed headlines recently as the open-source technology is now viewed as a hotbed for innovation. It is also a source of intellectual properties…
“Open ISAs (RISC-V, OpenPOWER, etc)” – Alistair Francis, Hugh Blemings (LCA 2021 Online) | linux.conf.auThe recent phenomenal growth of RISC-V and OpenPOWER proves that Open CPU architectures are no longer only an academic project but are a serious contender…
Securing RISC-V-Based Systems | Max Maxfield, Electronic Engineering JournalIn just a moment we are going to cogitate and ruminate over the question of how to secure our RISC-V-based systems, but first… Deep in…
Electronic industry trends for 2021 | Dunstan Power, newelectronicsThe world has never experienced such a year. With the global pandemic have come new norms for how we live such as a proliferation of…