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BSC, Codeplay and SiFive help accelerate applications on RISC-V thanks to V-extension support in LLVM
RiVer Core: A RISC-V Core Verification Framework
On-Board Decision Making in Space with Deep Neural Networks and RISC-V Vector Processors
Wanxiang Blockchain Organized the First Public Activity of RISC-V Blockchain SIG with Partners
Canonical Launches Its First Official Ubuntu RISC-V Builds, for SiFive’s Unleashed and Unmatched | Gareth Halfacree, hackster.io
Canonical Announces Ubuntu Support For RISC-V | Steven Dickens, Futurum
TII’s Secure Systems Research Centre Collaborates with Global Universities on RISC-V-Based Secure Flight Computer System
Video: RISC-V Ubuntu, Benchmarks and Gaming on the HiFive Unmatched | Tired Technician
SiFive Collaborates with Imperas on Models of SiFive’s RISC-V Core IP Portfolio
Automotive Hardware Functional Safety (FuSa) Features: ISO 26262
Ubuntu 20.04/21.04 64-bit RISC-V released for QEMU, HiFive boards | Jean-Luc Aufranc, CNXsoftLinux 5.13 Release – Notable changes, Arm, MIPS and RISC-V architectures | Jean-Luc Aufranc, CNXsoft
Seagate Announces Its Own RISC-V Cores for Future Storage Controllers | Joel Hruska, Extreme Tech
European R&D marks milestones in steps to deliver fully European platform for space applications | Cordis
Week In Review: Design, Low Power | Jesse Allen, Semiconductor Engineering
Green Hills adds RTOS support to portfolio of RISC-V-based SoCs | newelectronics
Seagate, Western Digital outline progress on RISC-V designs | Carol Sliwa, SearchStorage.TechTarget.com
Saifang Technology releases leading performance RISC-V Tianshu processor core (Chinese) | China News Network
Lattice Propel Accelerates Time-to-Market for Embedded Processor-based Designs on Latest Nexus Platform FPGAs | businesswire
Swiss AI Chip Startup Raises Seed Funding | Sally Ward-Foxton, EE Times
Cobham Advanced Electronic Solutions Introduces Support for Wind River VxWorks RTOS for NOEL-V Processor | Cobham
Après Western Digital, Seagate conçoit à son tour ses propres cœurs de processeur RISC-V (French) | Pierrick Arlot , L'embarqué
BSC, Codeplay and SiFive help accelerate applications on RISC-V thanks to V-extension support in LLVMThe Barcelona Supercomputing Center (BSC) has been collaborating with Codeplay Software and SiFive to implement support for the RISC-V V-extension v0.10 in the LLVM compilation infrastructure.…
RiVer Core: A RISC-V Core Verification FrameworkInCore and Tessolve announce the availability of our open source RISC-V Core Verification tool - RiVer Core. RiVer Core is a python based extensible and…
On-Board Decision Making in Space with Deep Neural Networks and RISC-V Vector ProcessorsStefano Di Mascio, Alessandra Menicucci, Eberhard Gill, Gianluca Furano and Claudio Monteleone Abstract The use of deep neural networks (DNNs) in terrestrial applications went from niche…
Wanxiang Blockchain Organized the First Public Activity of RISC-V Blockchain SIG with PartnersOn June 24, during the RISC-V World Conference China 2021 hosted by ShanghaiTech University, Institute of Software Chinese Academy of Sciences, CRVIC, CRVA and CNRV,…
Canonical Launches Its First Official Ubuntu RISC-V Builds, for SiFive’s Unleashed and Unmatched | Gareth Halfacree, hackster.ioPartnership with SiFive aims to make Ubuntu the "reference OS for early adopters" of Linux on desktop-class RISC-V. Canonical has confirmed official RISC-V support for…
Canonical Announces Ubuntu Support For RISC-V | Steven Dickens, FuturumCanonical announces Ubuntu operating system support for a new architecture, namely RISC-V. Working with RISC-V core IP designer and development board manufacturer, SiFive, Canonical announced…
TII’s Secure Systems Research Centre Collaborates with Global Universities on RISC-V-Based Secure Flight Computer SystemTechnology Innovation Institute (TII), the applied research pillar of Abu Dhabi’s Advanced Technology Research Council (ATRC), today announced that its Secure Systems Research Centre (SSRC)…
Video: RISC-V Ubuntu, Benchmarks and Gaming on the HiFive Unmatched | Tired TechnicianIn this video we explore getting Ubuntu installed on the HiFive Unmatched. Then we have a little fun with some benchmarks, followed up by trying…
SiFive Collaborates with Imperas on Models of SiFive’s RISC-V Core IP PortfolioImperas Software Ltd.,the leader in virtual platforms and high-performance software simulation, today announced that SiFive, Inc., the industry leader in RISC-V processors and silicon solutions, has…
Automotive Hardware Functional Safety (FuSa) Features: ISO 26262In all critical applications like aircrafts, medical equipment and automobiles, there is a requirement for the systems to be reliable and safe. These requirements are…
Ubuntu 20.04/21.04 64-bit RISC-V released for QEMU, HiFive boards | Jean-Luc Aufranc, CNXsoftLet’s a lot of excitement around RISC-V open architecture, but a lot of work still needs to be done to bring the ecosystem to level…
Linux 5.13 Release – Notable changes, Arm, MIPS and RISC-V architectures | Jean-Luc Aufranc, CNXsoftSo we had quite the calm week since rc7, and I see no reason to delay 5.13. The shortlog for the week is tiny, with…
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Seagate Announces Its Own RISC-V Cores for Future Storage Controllers | Joel Hruska, Extreme Techchips, which are not referred to by any codename or brand, come in two flavors: A high-performance core and an area-optimized core. The high performance core…
European R&D marks milestones in steps to deliver fully European platform for space applications | CordiseeNews Europe reports. Summing up in part with regard to hardware, a De-RISC post on its first anniversary says “the project has developed the first…
Week In Review: Design, Low Power | Jesse Allen, Semiconductor EngineeringRISC-V RISC-V International CEO Calista Redmond provided an update on the state of the community during the annual RISC-V Summit: “RISC-V has had an incredible year of growth…
Green Hills adds RTOS support to portfolio of RISC-V-based SoCs | newelectronicsGreen Hills Software has announced the availability of its safety certifiable µ-velOSity real-time operating system (RTOS) for RISC-V. Green Hills' µ-velOSity RTOS has provided…
Seagate, Western Digital outline progress on RISC-V designs | Carol Sliwa, SearchStorage.TechTarget.comSeagate unveiled its first two processors based on the free and open RISC-V instruction set architecture. One is a high-performance core built with RISC-V-enabled silicon…
Saifang Technology releases leading performance RISC-V Tianshu processor core (Chinese) | China News NetworkChina News Service, December 10th. With the accelerated development of artificial intelligence and Internet of Things technology, from the end to the cloud, the new application…
Lattice Propel Accelerates Time-to-Market for Embedded Processor-based Designs on Latest Nexus Platform FPGAs | businesswireBUSINESS WIRE)--Lattice Semiconductor Corporation (NASDAQ: LSCC), the low power programmable leader, today announced a new version of Lattice Propel™, a design environment for accelerating embedded processor-based development on…
Swiss AI Chip Startup Raises Seed Funding | Sally Ward-Foxton, EE TimesRISC-V SoC for AI processing in IoT devices. The company, a spin-off from the Institute of Neuroinformatics (INI) at the University of Zürich and ETH Zürich,…
Cobham Advanced Electronic Solutions Introduces Support for Wind River VxWorks RTOS for NOEL-V Processor | CobhamARLINGTON, Va. - Cobham Advanced Electronic Solutions (CAES), a leading provider of mission critical electronic solutions, announced at the RISC-V Summit the availability of Wind River’s…
Après Western Digital, Seagate conçoit à son tour ses propres cœurs de processeur RISC-V (French) | Pierrick Arlot , L'embarquéA l’occasion du RISC-V Summit qui se tient sous une forme virtuelle du 8 au 10 décembre, la firme américaine Seagate, spécialiste du stockage, a annoncé…