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PicoCom tapes out multicore RISC-V OpenRAN chip for ORANIC board | eeNews Europe, Nick Flaherty
VIDEO: RISC-V: The Lowest Layer of the Cloud-Native Landscape – Daniel Mangum & Carlos Eduardo de PaulaRISC-V中国峰会议程公开（非最终版本）
Coming June 2 – RISC-V Developer Tools and Tool Chains Forum! Register now!
RISC-V RV32I Instructions Format | Maven Silicon
Antmicro Develops RISC-V SoM | electropages, Robin Mitchell
What is RISC-V and Why is it Important? | ICS, Jeff Tranter
How does RISC-V fit into automotive systems? | EE World, Jeff Shepard
Five tips for writing RISC-V assembly code #RISCV | Stephen Marz
KubeCon EU: The Case for Bare Metal | B. Cameron Gain, The New StackKubern
Dialog Semiconductor Selected as SiFive Preferred Power Management Partner for RISC-V Development Platforms | Dialog SemiconductorRISC-V国际基金会现已登陆B站（哔哩哔哩）
Olof Kindgren: exclusive interview for AT | ArchiTechnologia
Hot Chips: Alibaba’s Ultra High-Performance Superscalar Processor – XuanTie910 | Embedded Computing Design
Alibaba’s Ultra High-Performance Superscalar Processor – XuanTie910 | Abhishek Jadhav, Embedded Computing Design
Program a Shakti RISC-V processor using Rust
IPFS on RISC-V | David Burela
First steps to European multicore RISC-V chip for space | Nick Flaherty, eeNews Europe
Emulating RISC-V Debian on WSL2 | David Burela
My New Research Project | Kian Nejadfard
Taking the mystery out of custom extensions in RISC-V SoC design | Embedded Staff
De-RISC First Anniversary, a H2020 Project Which Will Create the First RISC-V, Fully European Platform for Space
PicoCom tapes out multicore RISC-V OpenRAN chip for ORANIC board | eeNews Europe, Nick FlahertyUK chip designer PicoCom is taping out its core chip for OpenRAN wireless networks and developed a board-level product called ORANIC to speed up deployment.…
VIDEO: RISC-V: The Lowest Layer of the Cloud-Native Landscape – Daniel Mangum & Carlos Eduardo de PaulaDon’t miss out! Join us at our upcoming event: KubeCon + CloudNativeCon North America 2021 in Los Angeles, CA from October 12-15. Learn more at…
RISC-V中国峰会议程公开（非最终版本）计划于6月21日至26日举行的第一届「RISC-V中国峰会」，目前已经完成了征稿和评审，而大会的完整议程计划于本周公布。本次大会共收到演讲投稿130+篇，共接收 Keynote（主旨演讲） 、邀请报告超过16个，正式报告（20分钟）超过20个，简短报告约50个。大会本次根据投稿情况，在已有分类基础上为中科院计算所的香山RISC-V处理器（后续会开源）特别增设「香山Session」，接收12篇香山处理器的报告。对于开源RISC-V处理器感兴趣的伙伴千万不要错过。本次峰会的主会将从原计划三天扩充至四天，并且计划在6月24日至26日举办多个 workshop 和 tutorials 活动。目前已经接收超过15场同地活动的申请，包括 StarFive、芯来科技、Andes（晶心科技）、平头哥、全志等国内 RISC-V 知名企业都将在峰会期间举办技术沙龙。 峰会期间不仅有精彩的技术报告，主会场周边同时开放了大量展区，目前正在积极筹备阶段，欢迎到时候来现场逛一逛，感受一下RISC-V的热度。感谢本次峰会的赞助商及主办方，承担了本次峰会的全部费用。本次峰会不仅免收门票费用，峰会举办期间还会提供免费的茶歇和午餐饭票。由于目前仍处于疫情防御阶段，峰会主办方遵守上海市浦东新区防疫相关规定，目前开放共1500场次的门票，请感兴趣的小伙伴抓紧报名！ 报名链接（参会免费）： https://www.bagevent.com/event/7314534 请注意我们有可能根据疫情管控要求进行人员限流。报名成功后请留意手机短信通知。 （最后更新时间：2021年5月14日 - 请注意本议程尚在更新完善中，具体议程在5月21日演讲者提交最终版Slides后确认） 时间 星期二 · 6月22日 08:00 - 08:30 签到和社交…
Coming June 2 – RISC-V Developer Tools and Tool Chains Forum! Register now!The RISC-V Forums, hosted by RISC-V International, are short-form, single-topic, deep-dive virtual events. This is the spirit of RISC-V events – providing technical content to…
RISC-V RV32I Instructions Format | Maven SiliconThis video explains all RV 32I Instruction formats, R, I, S, B, J, and U types, and how it simplifies the instruction decoder logic. Follow…
Antmicro Develops RISC-V SoM | electropages, Robin MitchellRecently, Antmicro announced the release of its ARV module that integrates a RISC-V-based SoC and other supporting components. So what is RISC-V, what features does…
What is RISC-V and Why is it Important? | ICS, Jeff TranterWhen it comes to processor architectures, you're probably familiar with x86 and ARM, but have you ever heard of RISC-V? If not, you owe it…
How does RISC-V fit into automotive systems? | EE World, Jeff ShepardRISC-V is being used in a surprising range of automotive systems ranging from ASIL-D safety rated controllers and security co-processors, artificial intelligence (AI) accelerators, controllers…
Five tips for writing RISC-V assembly code #RISCV | Stephen MarzWriting assembly is itself an art. When C, C++, or any other language is compiled, the compiler determines the art of writing assembly. However, this…
KubeCon EU: The Case for Bare Metal | B. Cameron Gain, The New StackKubernThe great shift to the cloud has often “clouded” the critical role that on-premises infrastructure — and more specifically — bare metal servers can play…
Dialog Semiconductor Selected as SiFive Preferred Power Management Partner for RISC-V Development Platforms | Dialog SemiconductorDialog’s highly efficient, cost effective PMICs, deliver “Exact Fit” power solutions London, United Kingdom – May 11, 2021 – Dialog Semiconductor plc (XETRA:DLG), a leading…
RISC-V国际基金会现已登陆B站（哔哩哔哩）作为一个充满活力的文化社区和视频平台，哔哩哔哩（Bilibili）吸引着大量中国年轻一代的关注和追捧。为了提高 RISC-V 在国内的知名度，为国内 RISC-V 从业者和爱好者提供一个互动交流的平台，我们在 Bilibili 上开通了 RISC-V 国际基金会的账号，并上传了系列视频。后续会不定期更新RISC-V的相关内容，一起来关注我们吧。 我们的账号是：RISCV国际基金会，URL是： https://space.bilibili.com/1121469705/video 目前已经将 RISC-V 国际基金会在油管上的视频全部上传了。请大家多多关注，一键三连！ As an energetic cultural community and video platform, Bilibili attracts…
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Olof Kindgren: exclusive interview for AT | ArchiTechnologiaOlof Kindgren, a Swede high/low-level developer, open-source software an silicon advocate, and director of FOSSi Foundation, in addition to occasional blogger. He also has interesting…
Hot Chips: Alibaba’s Ultra High-Performance Superscalar Processor – XuanTie910 | Embedded Computing DesignXuantie-910 RISC-V core which is an ultra high-performance processor with an AI acceleration engine based on RISC-V RV64GCV. It has a remarkable performance of around 40%…
Alibaba’s Ultra High-Performance Superscalar Processor – XuanTie910 | Abhishek Jadhav, Embedded Computing DesignXuantie-910 RISC-V core which is an ultra high-performance processor with an AI acceleration engine based on RISC-V RV64GCV. It has a remarkable performance of around…
Program a Shakti RISC-V processor using RustOpen Source RISC-V processor development ecosystem created by researchers at IIT Madras. This post describes how you can get bare metal Rust running on a…
IPFS on RISC-V | David Burelamy excitement for RISC-V, with one of my goals to see if I can get a decentralised stack running on top of it. My first…
First steps to European multicore RISC-V chip for space | Nick Flaherty, eeNews EuropeRead the full article.]]>
Emulating RISC-V Debian on WSL2 | David BurelaI talked about my excitement for RISC-V. Since then I have been experimenting to see what I can do before getting my hands on real…
My New Research Project | Kian NejadfardRISC-V (pronounced "risk-five"), a free and open-source instruction set architecture, and my interest in open hardware, coupled with the fact that for RKern starting small…
Taking the mystery out of custom extensions in RISC-V SoC design | Embedded StaffA guide to accelerating applications with just-right RISC-V custom instructions.” In designing a system for many products today, power consumption, performance and die area constrain…
De-RISC First Anniversary, a H2020 Project Which Will Create the First RISC-V, Fully European Platform for Space“De-RISC, the Horizon 2020 project (EIC-FTI 869945) that aims to create a market-ready platform based on RISC-V for the aerospace market, celebrates its one-year anniversary."…